[time-nuts] GPS lock of the FE5680. Current experiment and question

[Bob Camp]

Hi

If you go to a sample and hold, just use it to capture the voltage of the 10 MHz sine wave. That is one way to do an analog phase detector...

Bob



On Feb 10, 2012, at 8:54 PM, David <davidwhess at gmail.com> wrote:

> Flip-flops hardened against metastability are available.
> 
> I would try a track and hold before a sample and hold but I wonder how
> accurate it would be having to rely on the oscillator waveform.  Fast
> sample gates are non-trivial.  I believe better than either would be a
> time to voltage converter which just needs a set/reset flip-flop and
> switched current integrator.  Dig up the schematic for a Tektronix
> 2232 oscilloscope for a "simple" example that yields 50pS resolution
> using late 1980s  technology.
> 
> I just recently ventured into the sampling oscilloscope world with a
> 7S11/S-4/7T11 setup.  The S-4 uses a traveling wave gate which avoids
> the fast sample gate problem but I would consider that the far side of
> esoteric since I have not studied it in detail yet.
> 
> On Fri, 10 Feb 2012 17:23:46 -0800 (PST), Robert LaJeunesse
> <rlajeunesse at sbcglobal.net> wrote:
> 
>> Sampling unsychronized signals with a DFF is problematic, since if setup and 
>> hold times are not met the output could oscillate and maybe settle to some noise 
>> driven value. I can't help thinking that if you are sampling the 10MHz signal at 
>> 1Hz the only way to get reasonable resolution is to sample the 10MHz sinewave 
>> signal's fastest part with tight analog sample & hold. Looking at the result wih 
>> a slow, low-cost 24-bit A to D chip would give tremendous resolution - if the 
>> drift was low enough. Use the ADC over a sub-range and add a small micro for 
>> noise filtering and averaging and one can achieve measurements result in the 10s 
>> of femtoseconds. 
>> 
>> ________________________________
>> From: David <davidwhess at gmail.com>
>> To: Discussion of precise time and frequency measurement <time-nuts at febo.com>
>> Sent: Fri, February 10, 2012 8:10:56 PM
>> Subject: Re: [time-nuts] GPS lock of the FE5680. Current experiment and question
>> 
>> All you need for this is the flip-flop.  Clock the flip-flop with the
>> 1 PPS signal and capture whether the oscillator is leading or lagging.
>> This requires the 10 MHz oscillator to be within 1 Hz but if you
>> divide it down before the comparison, you can extend this range as
>> needed to handle wider initial oscillator frequencies and larger
>> amounts of PPS jitter.
>> 
>> The simple GPSDO design in QST a couple years ago did something like
>> this.
> 
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