[time-nuts] Logging the grid frequency....
Tom Van Baak
tvb at LeapSecond.com
Thu Feb 28 11:37:38 EST 2013
I've placed two log files for you under http://leapsecond.com/pages/mains/
log1932.dat.gz -- timing of every 60 Hz zero-crossing (1.296 million samples)
log97312.dat.gz -- timing of every 60th zero-crossing (21.6 thousand samples)
Each represents 6 hours of collection time. Units are seconds (elapsed time), resolution is 100 ns, granularity is 400 ns. This data was collected with a picPET (http://leapsecond.com/pic) using an accurate 10 MHz reference.
This should be more than enough data to characterize the typical short-term noise and mid-term wander of the (US western) power grid. Of course, the power spectrum in Brazil will likely look different. I'd be interested in seeing your results.
----- Original Message -----
From: "Daniel Mendes" <dmendesf at gmail.com>
To: "Discussion of precise time and frequency measurement" <time-nuts at febo.com>
Sent: Thursday, February 28, 2013 6:08 AM
Subject: Re: [time-nuts] Logging the grid frequency....
Thanks for all the comments about this topic. They are much appreciated.
About the difficulty of measuring every cycle with a conventional
counter... thanks for that info, seems that i´ll have to make my own
measurement hardware. I liked the idea of a time stamping counter....
it´s very doable in a FPGA :)
About the fact that 60Hz mains have a lot of noise... I knew that and
that´s part of a PLL job (filter very fast noise), but unfortunately
when doing this measurement job we can only use analog filters or else
we´ll mess too much with the frequency... i´m using a transformer (to
isolate and to give some inductance) with capacitors to make a low pass
The PLL design is a wide band type.
Seems that frequency stays between 59,95Hz and 60,05Hz for 99,99% of the
time... that´s an interesting point too.
Em 22/02/2013 23:09, Bob Camp escreveu:
> A lot depends on what the real objective is. Is the loop supposed to transfer all of the 60 Hz bumps and wiggles (wide band loop) or is it supposed to ignore them (narrow band loop) ? Given that the starting point is 60 Hz wide and narrow will be relative to that.
> On Feb 22, 2013, at 7:44 PM, David <davidwhess at gmail.com> wrote:
>> On Fri, 22 Feb 2013 15:16:37 -0800, "Tom Van Baak"
>> <tvb at LeapSecond.com> wrote:
>>>> There is a lot of noise on the line. I'm not sure if frequency makes sense
>>>> on a cycle to cycle basis.
>>> Hal, it might make sense since the OP is designing a PLL and wants to get a feel for (short-term) frequency excursions. I would guess the whole point of his experiment is to quantify this; not just say there is "a lot" or "not much" noise over some number N of cycles.
>>> So that's why I posted the ADEV plot, which itself was based on timing every zero-crossing (using a time-stamping counter, not a frequency counter).
>> I have been thinking about this problem on and off all day and would
>> probably add a sampling phase detector driven by the output of the PLL
>> or just use a sampling phase detector in the PLL loop. The sampling
>> time can be adjusted independently of the PLL filtering within reason
>> for whatever level of noise rejection in the measurement is desired.
>> That would return the phase error on every cycle or even every half
>> The whole thing of course could be implemented digitally but I like
>> programming in solder.
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