[time-nuts] 10 MHz -> 16 MHz clock multiplier

EWKehren at aol.com EWKehren at aol.com
Thu Jan 3 09:57:26 UTC 2013


Ulrich
you beat me to it, we have been using lately the ICS 512 and 570 for some  
of our projects. If symmetry is not required 80 MHz and a 74 AC 90 will do, 
if  symmetry is a must  the only low cost way I know is 160  MHz and a $ 2  
MAX3000A gate array. We actually did a symmetrical divide by 3 and 5.
Bert Kehren
 
 
 
In a message dated 1/3/2013 4:11:45 A.M. Eastern Standard Time,  
df6jb at ulrich-bangert.de writes:

Tom,

my 50 cents are: Use a 1 Euro expensive ICS503 in a  SOIC package to 
generate
a 160 MHz signal from the 10 MHz without further  components needed (except
one c on the VCC and one on the input) and then  divide by 10. Expect a 50 
ps
one sigma jitter on the output. You MUST use  capacitive coupling with an
external oscillator. Easily breadboarded! Have  used such a configuration to
generate phase locked clock signals for older  FPGAs without internal clock
generation.

Best regards
Ulrich  

> -----Ursprungliche Nachricht-----
> Von:  time-nuts-bounces at febo.com 
> [mailto:time-nuts-bounces at febo.com] Im  Auftrag von Tom Van Baak
> Gesendet: Mittwoch, 2. Januar 2013  19:55
> An: Discussion of precise time and frequency measurement
>  Betreff: [time-nuts] 10 MHz -> 16 MHz clock multiplier
> 
>  
> What's the simplest way to generate 16 MHz from 10 MHz? This 
>  will be for clocking a microcontroller at 16 MHz given 10 MHz 
>  (Cs/Rb/GPSDO). Low price and low parts count is a goal; 
> jitter is not  a concern but absolute long-term phase 
> coherence is a must.
>  
> The ICS525 (as in TAPR Clock-Block) is a good candidate but I  
> was wondering if there's something cheaper, less functional, 
>  and maybe not SSOP. Any suggestions?
> 
> Thanks,
>  /tvb
> 
> 
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