[time-nuts] 10 MHz -> 16 MHz clock multiplier

David davidwhess at gmail.com
Fri Jan 4 02:22:49 UTC 2013


Oh, there are lots, well, at least some presetable synchronous
counters in fast logic families that could be used but that would
require extra glue logic.  Alternatively if you just want to divide by
5 or some other small fixed number, you can use a couple of flip-flips
and gates.

On Thu, 03 Jan 2013 21:02:32 -0500, "Tom Miller"
<tmiller at skylinenet.net> wrote:

>Isn't there a fast divide by N counter that you could set to 10? Maybe even 
>in ECL?
>
>
>----- Original Message ----- 
>From: "David" <davidwhess at gmail.com>
>To: "Discussion of precise time and frequency measurement" 
><time-nuts at febo.com>
>Sent: Thursday, January 03, 2013 8:49 PM
>Subject: Re: [time-nuts] 10 MHz -> 16 MHz clock multiplier
>
>
>They do not exist as I found out (again) not long ago.  The last 7490
>made was LS (low power schottky) and I use quite a few of them.
>Actually, I have seen a datasheet for a 74HC90 and 74HCT90 but they
>apparently either never went into production or very few were
>produced.
>
>The closest non-TTL alternative that I found was the 74HC390 or
>74HCT390 which is basically two 7490 counters in one package.
>
>On Fri, 04 Jan 2013 11:59:01 +1100, Max <vk3yba at gmail.com> wrote:
>
>>Where can one get some of these mythical  74HC90 's and 74AC90 's that
>>have been mentioned.
>>  None of the usual places have them, ie ebay, digi-key, farnell, or
>>even the Chinese.
>>  Also data-sheets are not to be found.
>>Thanks
>>
>>
>>
>>On 4/01/2013 5:13 AM, Bill Fuqua wrote:
>>>     One way is to divide by  10 and then multiply by 16.
>>> Divide by 10 and then follow by 4 tuned frequency doublers.
>>> This should introduce little phase noise.
>>>     Another way to do it is to divide by 10, then pass the output thru a
>>> narrow 16 MHz filter and amplify. Sounds difficult but the filter can
>>> be one
>>> or two 16 MHz crystals followed by a simple amplifier. Look at the
>>> reference input circuit for a PTS-160.  The output of the divide by 10
>>> needs to
>>> be asymmetrical so it produces even harmonics. If you are using a
>>> divide divide by 5&2 such as a 74HC90, divide by 2 first then by 5.
>>>  Ideally the pulse width should be a half period of 16 MHz for the
>>> maximum harmonic content at 16 MHz.
>>>     You can take the output of the frequency divider and send it to a
>>> NAND gate.
>>> One input of the gate is directly connected and the other is delayed.
>>> You can
>>> use an RC with a variable capacitor to ground to get it just right.
>>>     Just adjust the capacitor to get the maximum output from your
>>> filter amplifier.
>>> 73
>>> Bill wa4lav
>>>
>>>
>>>
>>> At 07:41 PM 1/2/2013 +0000, you wrote:
>>>> What's the simplest way to generate 16 MHz from 10 MHz? This will be
>>>> for clocking a microcontroller at 16 MHz given 10 MHz (Cs/Rb/GPSDO).
>>>> Low price and low parts count is a goal; jitter is not a concern but
>>>> absolute long-term phase coherence is a must.
>>>>
>>>> The ICS525 (as in TAPR Clock-Block) is a good candidate but I was
>>>> wondering if there's something cheaper, less functional, and maybe
>>>> not SSOP. Any suggestions?
>>>>
>>>> Thanks,
>>>> /tvb



More information about the time-nuts mailing list