[time-nuts] looking for low-power system for gps ntp timekeeping

[Hal Murray]

mc235960 at gmail.com said:
> Is that what you really want? In most modern x86 CPU's you have a TSC which
> is a 64bit counter incremented at the cpu clock cycle speed . You can
> capture that with a single instruction. NTP uses that if it is available.
> So to get an accurate TI you just take 2 samples and subtract. You just need
> to take into account interrupt handling latency. I don't think this is
> available in ARM under that name, but there is a cycle count register CCNT
> which does the same thing. I think it is 64 bit as well. 

The problem is that there is a lot of noise in the interrupt handling.  It's 
things like cache faults.  At the 10s of microsecond level, it probably 
doesn't matter much.  Below that, things get interesting.

SOC type chips (mostly ARM) usually have some sort of counter/timer gizmo 
with a register that gets loaded (before any interrupt) when an external 
signal changes.  That change can also generate an interrupt and the interrupt 
handler can read the register.  It works great for PPS type stuff.



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