[time-nuts] Thunderbolt tuning DAC theory of operation
John C. Westmoreland, P.E.
john at westmorelandengineering.com
Mon Nov 4 21:21:33 EST 2013
Stu,
I read this basically when it was posted.
I would like to thank you for posting this. The theory on how to
discipline an OXCO is something that I want to learn more about - and posts
like this help with that
a lot.
So, thank you Stu - much appreciated!
Best Regards,
John Westmoreland
On Sat, Nov 2, 2013 at 1:41 AM, Stewart Cobb <stewart.cobb at gmail.com> wrote:
> While poking around the Thunderbolt to determine whether -5V could be
> used in place of -12V, I discovered how the OCXO tuning DAC works.
> Apologies if this is old news, but I haven't seen it documented
> before.
>
> The 10MHz sine wave from the OCXO is squared up and used to clock the
> Xilinx 5200 CPLD (U22) and a 74AC174 hex D flip-flop (U14). Inside
> the CPLD (apparently) the 10 MHz clock is divided by 1024, giving a
> square wave with a period of 102.4 us (about 9.7 kHz). The duty cycle
> of that square wave is modulated by the 10 MSBs of the commanded DAC
> value. The LSBs are used to offset the falling edge of the square
> wave one clock cycle (100 ns) later, during a fraction of the 9.7 kHz
> square waves proportional to the LSBs value. On a modern digital
> scope, you can zoom in on the falling edge of the square wave, set the
> display to "average", and see that the averaged height of that clock
> cycle is proportional to the DAC LSBs. There appear to be at least 8
> LSBs, perhaps as many as 10, giving a total DAC resolution of 18 to 20
> bits. (If the DAC value is averaged over one second, there are 10^7
> clock cycles which can be controlled, giving a theoretical maximum
> resolution of 23+ bits. Trimble may have chosen a shorter averaging
> time and fewer bits.)
>
> The PWM square wave travels from pin 13 of the CPLD (U22) to pin 4,
> the D1 input of the 74AC174 (U14). The flip-flops in this chip are
> also clocked by the squared-up 10 MHz from the OCXO. The Q1 output,
> pin 5 of U14, goes to one side of R83 in the circuitry around the
> LT1014 op-amp. The other five inputs and outputs of U14 are
> constantly high or low. They may also be fed to the op-amp circuits,
> to help it handle the square wave in a purely ratiometric manner.
>
> The inputs and outputs of the Xilinx CPLD can be programmed for many
> different I/O standards. Unfortunately, this makes their output pin
> drivers far from ideal. The purpose of the 74AC174 is presumably to
> drive the analog circuitry with a input that is as close as possible
> to a mathematically ideal digital signal. Outputs in the 74AC logic
> family can source or sink 24 mA and have relatively balanced raise and
> fall times. This was probably the most ideal digital output available
> to the Thunderbolt's designers in the late '90s.
>
> This DAC implementation is guaranteed monotonic, an important
> consideration. There is exactly one rising edge and one falling edge
> per cycle, so that any difference between rise and fall times will
> have a constant effect which can be tuned out. Unlike a sigma-delta
> DAC, this PWM DAC produces strong spectral lines at multiples of the
> 9.7 kHz square wave frequency. On the one hand, it is comparatively
> easy to design filters to remove a single frequency (and its
> harmonics). On the other hand, this signal is strong enough that it
> may appear in phase noise plots anyway.
>
> If you want to view the 9.7 kHz square wave for yourself, it appears
> on a small square test point next to the silkscreen designator for
> C78, very close to the 6-pin power input jack. This test point is
> part of the connection from the Xilinx CPLD to the hex D flip-flop.
> Probing it does not affect the OCXO tuning.
>
> Hope this helps.
>
> Cheers!
> --Stu
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