[time-nuts] Trimble 34310-T EFC Question

[Bob Stewart]

From: Charles Steinmetz <csteinmetz at yandex.com>
"It is common to use an additional, external series resistor and shunt 
capacitor, generally 10-50k and anywhere from 0.01uF to tens or even 
hundreds of uF, depending on the application.  Of course, this 
additional pole needs to be taken into account in the loop stability analysis of the PLL."


Thanks Charles,

My exposure to this stuff is extremely limited, and this is a big help!  I can plug this into LTSpiceIV and hopefully wind up with something that works at all ranges of this dithered PWM derived DAC.

Bob




>________________________________
> From: Charles Steinmetz <csteinmetz at yandex.com>
>To: Discussion of precise time and frequency measurement <time-nuts at febo.com> 
>Sent: Thursday, November 7, 2013 5:09 AM
>Subject: Re: [time-nuts] Trimble 34310-T EFC Question
> 
>
>Bob wrote:
>
>> I think I may need to change the LPF feeding the EFC in my GPSDO to get rid of dithering jitter.  Is there any point in adding a resistor and cap in the EFC line, or do I need to go back and change the values in the op-amp circuit feeding it?  Currently an op-amp directly feeds the EFC pin.  I guess this boils down to something like: is there any meaningful current flow in EFC circuit in this oscillator?  Or should I add them but will I probably have to change the existing filter, as well?
>
>Generally, an EFC pin connects internally to one or more varicap diodes, which by definition must be reverse biased (thus, the only current flow is the reverse current (leakage) of the diode(s)).  There is often an internal series resistor of 50-100k between the EFC pin and the diode(s).  It is common to use an additional, external series resistor and shunt capacitor, generally 10-50k and anywhere from 0.01uF to tens or even hundreds of uF, depending on the application.  Of course, this additional pole needs to be taken into account in the loop stability analysis of the PLL.
>
>Best regards,
>
>Charles
>
>
>
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