[time-nuts] LNA and Alias

[Bob Camp]

Hi

The nature of a ADC with a built in digital front end filter is to have multiple passbands centered around the ADC clock and it’s harmonics. Put another way - the chip has zero rejection at clock * N where N = 1,2,3,4,5…. They may also have zero rejection at other frequencies (like clock / 2) depending on the sampling architecture. 

If you are trying to look for spurs in the -120 dbc range, RF at clock * N will have to be ~ 120 db down. In this case, “down” is relative to the roughly 1 V output from the mixer. That equates to less than one microvolt of RF running around at the input to the ADC if the preamp gain = 1. If your preamp is running at 60 db of gain, you would need to be below 1 mv of RF at the input to the ADC. Since conversion at the harmonics may or may not be perfect and since phase noise goes up by 20 log (N) the attenuation needed is only approximate. It’s likely within 10 or 20 db either way. 

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One simple solution is to move the ADC clock far enough away from 10 MHz * N so that the beat notes are outside the region you are looking at phase noise. If you are trying to go to 100 KHz, then a clock that is a bit over 1% high or low would do the trick. The beat note is there, you just don’t care about it as much. You can’t tolerate a note that overloads the ADC, so some filtering is still needed. You also need to be careful that the close in noise does not wrap around and mess up your 100 KHz numbers. Again the solution is to have some filtering. You can go to a much larger clock offset that 1%. The risk there is that something like the 10th harmonic gets you in trouble. 

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Another “simple” solution is to just lock the ADC clock to your DUT. You still need some filtering so that the noise from the higher frequency images does not mix down and add to much to the floor. The same issues with overload would still apply as well. 

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Lots to play with.

Bob




> On Dec 26, 2014, at 8:37 AM, Loïc Moreau <loic.moreau at eai.fr> wrote:
> 
> Hi,
> 
> I have just found the culprit 
> 
> The AD7760 eval board in charge of the ADC task, is equipped with a little 40 MHz clock witch seems to generate a beat note with my 10Mhz noise measurements setup. I have discovered the origin of the problem after disconnecting the LNA from the  measurement chain and visualizing the output of the LNA with a scope.
> 
> The beat note was clearly visible, 10mV peak-peak . After shutting down every 10Mhz sources in my lab (a huge task) and altering the frequency of my phase noise measurement setup noise floor, I noticed that the low frequency noise was in fact a beat note following the ref frequency adjustments. ( The ref OCXO was replaced with a 33521A to alter amplitude and frequency at will) . 
> 
> As soon as I fire up the 7.5V power supply of the eval AD7760  (the eval card is not connected to anything). the LNA give a steady 10mV beat note as the 40 MHz clock seems mixing up somewhere a few herz apart from the regular source, polluting the close in phase noise measurements .
> 
> So after weeks of questioning, I was a bit disappointed to find out that the AD eval board, the least suspected item was at the origin of the problem. 
> 
>  Now, I have to address it . I have noticed the presence of smb connectors on the eval card, so I may substitute the internal clock, and a shield enclosure may cure that little beast.  At last DC power supply wires may also be substituted by shielded cable  just in case.  
> 
> I am relieved 
> 
> Regards.
> Loïc
>