[time-nuts] TIC model

Bruce Griffiths bruce.griffiths at xtra.co.nz
Tue Feb 18 22:35:10 EST 2014


The attached circuit schematic illustrates how this might be implemented.
Faster logic devices can be substituted.

R2, C2 approximate the equivalent input circuit of the ADC.
R2, C2 values will vary for each ADC.

The Shift register which acts as a synchroniser and produces various 
trigger signals is clocked at 10MHz (assumed to be the uP instruction 
cycle clock rate)

The RC network charge time varies between 1 and 2 shift register clock 
periods ( ie a charge time from 100ns to 200ns).
Sampling a time stamp counter clocked at the same frequency as the shift 
register is only required if the GPSDO local oscillator has a potential 
initial offset of  100ppb or more.
If missing PPS detection is required then a PPS time stamp counter with 
a range of several seconds is desirable.

Bruce

Bruce Griffiths wrote:
> Another variation is to use a single 125 style buffer device (eg 
> 74LVC1G125) to charge and discharge a capacitor (in reality an RC 
> network when the ADC input is taken into account) via a series resistor.
> The input to the buffer is driven by the input to a conventional 
> synchroniser whilst the buffer output enable is driven by the 
> synchroniser output.
> The buffer output being enabled whilst the synchroniser output is low 
> (for a 0-> 1 PPS input transition) and disabled whenever the 
> synchroniser output is high.
> This ensures that the capacitor network is discharged to zero between 
> PPS events without requiring an additional device (or a resistor) to 
> discharge the RC network.
>
> The capcitor reset level sensitivity to leakage currents is greatly 
> reduced over that when a 1M discharge resistor is used.
>
> The nonlinearity can be calibrated by using a statistical fill the 
> buckets technique.
> This requires a relatively noisy test signal generator (RC 
> oscillator??) to drive the synchroniser input.
> However its essential to ensure that this oscillator isnt injection 
> locked to the synchroniser clock.
>
>
> Bruce
>
> Lars Walenius wrote:
>> Hi Bruce
>>
>>
>>
>>
>> You are absolute right that it is wise to put some time in the 
>> estimation of such effects as asynchronous Clocks. An iteration 
>> between  thinking and building seems always to be necessary but we 
>> all have different capabilities for that. For the Arduino I came to 
>> an end with the interrupts as I am not good at uP´s.
>>
>>
>>
>>
>>
>>
>> The Arduino GPSDO has two interrupts. One is synchronous with the 
>> 10MHz and comes from timer1 overflows. The other is synchronous with 
>> the 1PPS. So it is three asynchronous clocks right now in the GPSDO 
>> controller.
>>
>>
>>
>>
>> As I understand my problem it is that an interrupt takes some time to 
>> execute and if you get the two interrupts to close you will have a 
>> problem with timing as you can´t execute both at the same time?
>>
>>
>>
>>
>> Of course the easy solution could be to have the needed resoulution 
>> higher than the time it takes to execute the interrupts but in the 
>> GPSDO I want a resolution of 200ns (5MHz Clock) and the shortest 
>> interrupt is 3us.
>>
>>
>>
>>
>> I would be glad if somebody (Chris?) could have a look in the Aduino 
>> GPSDO code to see if it possible to get rid of the uncertainty due to 
>> the interrupts from the timer1 overflow.
>>
>>
>>
>>
>> Another question: Does a PIC not need overflow interrupts to count 
>> say 5000000 counts as I do in the Arduino?
>>
>>
>>
>>
>> Lars
>>
>>
>>
>>
>>
>> From: Bruce Griffiths
>> Sent: ‎söndag‎ den ‎16‎ ‎februari‎ ‎2014 ‎20‎:‎14
>> To: time-nuts at febo.com
>>
>>
>>
>>
>>
>> The response time to an external asynchronous interrupt is never
>> deterministic.
>> The external interrupt has to be synchronous with the uP clock to avoid
>> the non deterministic synchronisation delay.
>> Even when the external event is synchronous with the clock input to the
>> uP and the uP uses a divider to produce its internal clock then there is
>> the issue of divider phase shift.
>> This phase shift can lead to sampling the waveform before the peak
>> across the sampling cap. This is far from ideal, its better to sample at
>> or slightly after the peak when the sensitivity to timing variations is
>> far smaller.
>> To complicate the issue further the time of occurrence of the peak is
>> temperature dependent and the sampling switch on resistance is nonlinear
>> so that peak delay varies with temperature and input signal amplitude.
>>
>> Its generally quicker and cheaper to estimate the magnitude of such
>> effects and make appropriate choices than just build a sequence of
>> breadboards each of  which then needs to be extensively characterised.
>>
>> Bruce
>>
>> Chris Albertson wrote:
>>> You all are "inventing problem".  Solve them AFTER you find a 
>>> problem you
>>> can measure.   Interrupts are not an issue on a UP like the AVR because
>>> they are completely deterministic.  It don't matter the lenth of 
>>> time as
>>> long as it is 100% deterministic and predictable.   On a 
>>> multi-tasking OS
>>> running on a super scaler CPU you have unknowable latentcy but this 
>>> is not
>>> the problem on a chip that does one machine cycle per clock cycle.
>>>
>>>
>>> On Sat, Feb 15, 2014 at 6:50 PM, Brian Lloyd<brian at lloyd.com>   wrote:
>>>
>>>
>>>> On Sat, Feb 15, 2014 at 7:10 PM, Tom Van Baak<tvb at leapsecond.com>   
>>>> wrote:
>>>>
>>>>
>>>>> For Arduino and other less fortunate uC you can always use 
>>>>> external chips
>>>>> to obtain optimal and jitter-free charge/discharge timing. I'm not 
>>>>> that
>>>>> familiar with Atmel chips; could capture/compare be used instead of
>>>>> interrupts somehow?
>>>>>
>>>>>
>>>> One should investigate the Propeller.
>>>>
>>>> -- 
>>>> Brian Lloyd, WB6RQN/J79BPL
>>>> 706 Flightline Drive
>>>> Spring Branch, TX 78070
>>>> brian at lloyd.com
>>>> +1.916.877.5067
>>>> _______________________________________________
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>>>>
>>>>
>>>
>>>
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>
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