[time-nuts] 'CPLDs for clock dividers' Thread
Tom Minnis
Tom_minnis at att.net
Sun Jan 5 23:29:12 EST 2014
I am working on a PLL design that uses the Lattice MX02-256 for the
dividers and XOR phase detector. I have not made any measurements on it
yet but will report back when it happens.
On 1/5/2014 7:37 PM, Hal Murray wrote:
>> I was looking at the archives - what was the outcome of this:
> What level of nuttiness are you interested in?
>
> CPLDs or FPGAs are neat because you can toss all sorts of stuff into them.
> If you do that, you introduce opportunities for power supply level noise
> coupling.
>
> If you have something simple like a divide by 2 or divide by 10 with no other
> logic in the chip, I'd expect the output to be clean. If you want to do a
> divide by 2 AND 10, I'll bet you will see some coupling. (at least if you
> look hard enough)
>
> Fine print:
> One buzzword to look for is SSO - Simultaneous Switching Output. The basic
> idea is that there is slight inductance/resistance in the power/ground
> connections and on chip power/ground distribution. If 2 signals switch at
> the same time, they share that and will be slightly slower than only one
> signal switching.
>
> You will probably get better results if your output PIN is next to pwr/gnd
> pins. (lower on-chip resistance)
>
> You may be able to help things by setting up nearby pins as outputs and
> wiring those pins to pwr/gnd and driving them with the appropriate logic
> level. The idea is to add semi-pwr pins. The resitance through the driver
> transistors is small enough so that it helps.
>
> It would be fun to measure some of that stuff.
>
>
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