[time-nuts] Divide by five
Neil Schroeder
gigneil at gmail.com
Sun Nov 9 02:13:41 EST 2014
Go on - actually stepping or mixing then filtering the output? Or
numerically deriving an offset?
I am well on my way to en ensemble of sources - and my plan has always been
to build a diverse set of circuits and attempt to capture the best of
each. I just wasn't sure the best approach.
At one point I was considering phase locking all of them together - but
again that seemed less than straightforward. You can do it PLL back to
back, but is there a way to have a loop that contains multiple clocks? I
would think the "telephone game" would apply.
NS
On Sat, Nov 8, 2014 at 6:35 PM, Bob Camp <kb8tq at n1k.org> wrote:
> Hi
>
> One of the more interesting uses for something like a Cyclone V would be a
> front end board to drive a KS-24361 from an ensemble of sources. That’s
> what David Allan’s original idea was when he started the whole software
> empire that turned into the Z3801 and all the rest.
>
> Bob
>
> > On Nov 8, 2014, at 8:36 PM, Bert Kehren via time-nuts <
> time-nuts at febo.com> wrote:
> >
> > We do most our projects with Altera G/A.
> > The biggest benefit is that if something does not work on first pass
> > changing the G/A logic is much faster, less costly than a new board
> layout.
> > Bert Kehren
> >
> >
> > In a message dated 11/8/2014 6:17:29 P.M. Eastern Standard Time,
> > kb8tq at n1k.org writes:
> >
> > Hi
> >
> > I’ve done a lot of designs with Altera parts. They are fine parts, but
> > they are not magic. On the CPLD parts, be careful of the speed grade
> and be
> > sure you do a timing analysis on your design before you buy any
> hardware. All
> > the design tools are schematic entry capable and free on the web.
> There’s
> > not a big speed bump when you start using them (like say needing to go
> > learn VHDL…).
> >
> > Once you get using them, the CPLD's are quite handy for a wide range of
> > projects, way beyond a simple divide by 5. Their bigger cousins (the
> FPGA’s)
> > aren’t that much more (under $35) and they will do a LOT, especially in
> the
> > newer series. The Cyclone 2’s had a minimum rated PLL input of 20(?)
> MHz.
> > The later parts bumped that down to 10 MHz. Much more TimeNuts
> compatible.
> >
> > Bob
> >
> >> On Nov 8, 2014, at 5:58 PM, cfo <xnews5 at luna.dyndns.dk> wrote:
> >>
> >> On Sat, 08 Nov 2014 09:58:36 +0100, Francesco Messineo wrote:
> >>
> >>>
> >>> can anyone suggest a (cheap if possible) programmer and software for
> >>> these modern PLD?
> >>>
> >>> Thanks and best regards Frank IZ8DWF
> >>
> >> I'd suggest ALTERA parts , but only because they are the cheapest
> boards
> >> on *bay , XILINX boards are 2 x the Altera price on *Bay.
> >>
> >> An EPM240 CPLD Board $9 (240 cells let you do quite a lot)
> >> http://tinyurl.com/qcusb69
> >>
> >> There's also an EPM-570 Board , but the price is almost the same as the
> >> below FPGA , and then the FPGA is the thing to get.
> >>
> >>
> >> A CycloneII EP2C5T144 FPGA board (With 2 onbard PLL's) $18 - Super
> value
> >> for the money
> >> http://tinyurl.com/pd326ct
> >>
> >> An ALTERA Programmer $6
> >> http://tinyurl.com/po2qhq2
> >>
> >>
> >> The only caveat is that they are NOT 5v tolerant , they can do 3v3 or
> >> less.
> >>
> >>
> >> ALTERA has the free QuartusII WEB Edition , and it works fine under
> both
> >> Windows & Linux (i'm using Mint17 x64 ... Ubuntu 14.04 based "under the
> >> hood")
> >>
> >> I am a VHDL beginner , and completed this (free) course s few month
> back
> >>
> >> Course
> >> http://tinyurl.com/per8lm5
> >>
> >> Forum
> >> http://tinyurl.com/pw3b9bv
> >>
> >>
> >> I have just did a divide by 5 with the EP2C5T144 FPGA board , using one
> >> of the PLL's. I did use so few resources, that it reported 0% of the
> > 4608
> >> Cells utilized, and 1 of 2 PLL's used.
> >>
> >> *********** SNIP *************
> >> Fitter Status Successful - Sat Nov 8 23:11:59 2014
> >> Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 SP 1 SJ Web
> >> Edition
> >> Revision Name div5pll
> >> Top-level Entity Name div5pll
> >> Family Cyclone II
> >> Device EP2C5T144C8
> >> Timing Models Final
> >> Total logic elements 0 / 4,608 ( 0 % )
> >> Total combinational functions 0 / 4,608 ( 0 % )
> >> Dedicated logic registers 0 / 4,608 ( 0 % )
> >> Total registers 0
> >> Total pins 6 / 89 ( 7 % )
> >> Total virtual pins 0
> >> Total memory bits 0 / 119,808 ( 0 % )
> >> Embedded Multiplier 9-bit elements 0 / 26 ( 0 % )
> >> Total PLLs 1 / 2 ( 50 % )
> >> *********** SNIP *************
> >>
> >> Actually i like Xilinx ISE WebPack better , but the cheap
> > *Bay/Aliexpress
> >> boards are ALTERA Boards , so i have both tools installed on my linux
> >> machine.
> >>
> >>
> >> If you don't feel like learning VHDL or Verilog , you can do the layout
> >> in "Schematic". ALTERA QuartusII does have an extensive 74xx lib built
> > in
> >> the schematic engine.
> >>
> >> See my ansver to assignment 10 , for a QuartusII schematic entry of a
> > 50M
> >> divider. Using use 4 x HC390 dividers in a divide : 100 / 100 / 100 /
> 50
> >> configuration.
> >> http://tinyurl.com/ntdkcst
> >>
> >>
> >> Be sure to get these versions of the tools , as both have upgraded
> their
> >> tools , and the new tools doesn't support the older (cheaper chips).
> >>
> >> Altera QuartusII : Version 13.0sp1 (13.1+ doesn't suport the old
> > CPLD's)
> >> Xilinx ISE : Version 14.7 (Vivado doesn't support the old stuff)
> >>
> >>
> >> I suggest to try it out , you can do a lot of logic in a 240 Cell CPLD
> ,
> >
> >> and MUCH more in the FPGA.
> >>
> >> The 4 x HC390 used 16% of the EPM240 logic , and it is less than 1% in
> >> the FPGA. As seen below.
> >>
> >> *********** SNIP ***************
> >> Flow Status Successful - Sat Nov 8 23:56:46 2014
> >> Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 SP 1 SJ Web
> >> Edition
> >> Revision Name lesson10d
> >> Top-level Entity Name lesson10d
> >> Family Cyclone II
> >> Device EP2C5T144C8
> >> Timing Models Final
> >> Total logic elements 39 / 4,608 ( < 1 % )
> >> Total combinational functions 39 / 4,608 ( < 1 % )
> >> Dedicated logic registers 31 / 4,608 ( < 1 % )
> >> Total registers 31
> >> Total pins 3 / 89 ( 3 % )
> >> Total virtual pins 0
> >> Total memory bits 0 / 119,808 ( 0 % )
> >> Embedded Multiplier 9-bit elements 0 / 26 ( 0 % )
> >> Total PLLs 0 / 2 ( 0 % )
> >> *********** SNIP ***************
> >>
> >>
> >> CFO - Denmark
> >>
> >> --
> >> E-mail:xnews5 at luna.dyndns.dk
> >>
> >> _______________________________________________
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