[time-nuts] Phase microstepper designs?
Poul-Henning Kamp
phk at phk.freebsd.dk
Thu Dec 10 03:36:02 EST 2015
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In message <05EA571F-18CD-4046-B520-63F29A8922A3 at n1k.org>, Bob Camp writes:
>> See also http://leapsecond.com/pages/fe405/ and the links near the bottom. This (patented) FEI design avoids the spur issues several of you have been talking about: the RF output comes from a low-noise VCXO not the low-drift OCXO+DDS itself.
>>
>
>It avoids the far removed spurs. If you have a close in spur, it passes right through the PLL loop and messes up your ADEV.
>Yes, this really does happen on real gear in the real world …..
Going (almost) 5MHz -> 15 MHz -> 15MHz is just asking for low frequency
trouble.
If I were to design such a product, I would pick the stable OCXO to have
a frequency well removed from the target frequency on as many decimal
digits as possible.
3.1415926535... MHz if I could get away with it.
--
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
phk at FreeBSD.ORG | TCP/IP since RFC 956
FreeBSD committer | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.
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