[time-nuts] Good references on holdover?

Javier Serrano javier.serrano.pareja at gmail.com
Fri Feb 6 08:31:39 EST 2015


Thanks for your ideas.

On Fri, Feb 6, 2015 at 11:09 AM, Hal Murray <hmurray at megapathdsl.net> wrote:
> Is your PLL analog or digital?  I'll assume digital since it's hard to hold
> analog voltages stable for several seconds.

Yes, it is digital. It's even software. It runs on an LM32 [1] soft
core inside an FPGA. Then there's a DAC and a VCXO. Our goal is to
achieve sub-ns synchronization with respect to a master reference even
during switch-over between redundant paths.

Cheers,

Javier

[1] http://www.ohwr.org/projects/lm32


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