[time-nuts] Newbie question

[Mike Monett]

>Hi Time-Nuts:
>Not sure what the protocol is here but I'll just jump in.

>I've just purchased an HP53310a modulation domain analyzer. Most you already know that these amazing instruments are basically a TIC with a graphic display of frequency vs time. I've always wanted one to record PLL settling time. I also know they are pretty non-intuitive to setup and use. Now that I have one I'd like to connect with someone that has experience using them.

>Anyone?

>Best Regards to the group.

>Stuart Rumley

>650-369-0575

>Hi Stuart,

>Also contact Joe Geller, who was active on time-nuts some years ago, and who wrote the ultimate 53310a reference page: http://www.gellerlabs.com/hp53310a.htm

>/tvb

One thing that Joe Geller doesn't mention is the fierce leakage from the
power transformer. You may not notice it on a modern scope with LCD
display, but my 53310A spewed so much field that it demolished the display
on a Tek 2467B sitting nearby. I had to move the 53310A to a separate
bench. Why it didn't seem to bother its own internal crt is a complete
mystery. I'm sure it would bother a Rubidium.

I found the 53310A to be a lot less useful than expected. There are other
ways of making measurements that are easier and more accurate. Now, it just
sits in a corner gathering dust.

As far as measuring the PLL settling, you will need an external reference
that you can frequency modulate. Depending on your requirements, it could
be something simple like an RC oscillator with lots of phase noise, or two
low phase noise OCXO's at slightly different frequencies with a digital
mixer detecting the phase alignment and switching the signal to your PLL
from one OCXO to the other.

You can monitor the VCO DC error voltage to look for risetime and ringing
problems. To monitor settling time, trigger the scope on the frequency
switch, delay out to the desired region, and display the reference and VCO
signals to the phase detector added together. If you use a triggered delay
you can step from one cycle to the next and watch the signals align
themselves.

Depending on the skill of the designer, the PLL may exhibit jumps in phase
during settling due to crosstalk, or many other kinds of nasties at
different points in the phase relationship. If he did not monitor the PLL
settling during development, there will likely be things you may not like.

Bottom line is I much prefer looking at the VCO DC error and the inputs to
the phase detector rather than trying to investigate these problems with
the 53310A. The actual waveforms give a lot more information to work with.

Mike Monett