[time-nuts] Using CPLD/FPGA or similar for frequency divider
attila at kinali.ch
Tue Jun 2 18:07:43 EDT 2015
On Tue, 2 Jun 2015 14:13:04 +0100
"David C. Partridge" <david.partridge at perdrix.co.uk> wrote:
> Is this a sensible thing to consider doing?
> Or would I be better sticking to AC/HC/AHC/LVC logic?
It depends ;-)
For most things it should be ok. You can reach lower levels of noise
with single 74xxx parts as you will have lower interference between
different parts of the circuitry. But how much better it might be
and whether other effects might actually make the "discrete" solution
worse, i cannot say.
For some rule of thumb guide lines, the poster/paper by Caloso
which he presented at EFTF last year where they measured noise
parameters of 4 different FPGA families. The main result is that
"the larger the better" is also true for low noise logic gates,
but there are outliers.
"Phase noise jitter in digital electronics", by Calosso and Rubiola, 2014
There is quite some data missing there, but I guess they hit the
page limit of the paper. Also testing different FPGA families would
be quite nice.
< _av500_> phd is easy
< _av500_> getting dsl is hard
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