[time-nuts] Using CPLD/FPGA or similar for frequency divider

Bob Camp kb8tq at n1k.org
Sat Jun 6 11:41:26 EDT 2015


Here’s an example:



There are other outfits that make similar parts that are at least as good. This is considered a
low end chip right now. The part on the demo board is a mid point for the part size wise. 

It will run 400 MHz clocks without much bother at all. It also is quite happy doing multiple modulo
divides to take those clocks down to multiple  1 pps outputs *and* have a load function on the
counter. You have enough room to use them as time tags on inputs to the FPGA and store a few
hours worth of data in memory. 

Can you do better with a faster part? sure can. Can you find cheaper parts? yes again. Is there
a competitor’s part that will do it cheaper / faster / easier (pick one) - most certainly. 

If you can enter a schematic into free software, you can design a pps divider with a part like this. 
No need to learn a programming language to work with one. The process is roughly the same as
learning a new pcb layout tool. Yes it runs on Linux and on Windows. 

I can’t buy the parts on the demo board for what they sell the board for. I can’t buy an 8 -10 
layer board that size in single piece for what they sell the demo board for. I can’t get it assembled
(BGA’s …) in one piece for what they sell the demo board for. I also can’t do multiples 
of that counter with discrete logic on a board that size. I also can’t buy all the chips that a 
counter that fast going that low would require (plus the board) for what the demo board 
costs. Bottom line, to use them, just buy them already on a board and mount that on 
whatever you are doing. 

No I’m not trying to sell you that demo board. I’m also not trying to convince you that there is one
and only one family of parts that are worth using. The point is - the world started going over to
FPGA’s in the mid 1980’s. Discrete logic design started to die out with ASIC’s in the early 1970’s.
For large scale stuff it was dead by the end of the 1970’s. Forty years later, there are very few 
places (other than i/o) that discrete gates get used. 

The world has changed a lot since the 1970’s. Design any UART’s with discrete logic since about 1971?


> On Jun 5, 2015, at 11:19 PM, Hal Murray <hmurray at megapathdsl.net> wrote:
> richard at karlquist.com said:
>> I used a CPLD in a 900 GHz (that's right 900 GHz) optical sampling scope
>> timebase.  It was great because you just write a 17 bit counter in VHDL and
>> there it is.  You don't have to know anything about building digital
>> hardware any more (40 years of experience wasted). Nobody cares about look
>> ahead carry, etc. 
> Is that really true?  Or perhaps, what fraction of the digital design space 
> does it apply to?
> How fast was your counter running?  How fast would it run?  Was it a simple 
> counter or was there enable/up/down/load type gating involved?
> What would you have done if you needed to run a bit faster?  Could you buy a 
> faster chip?  How much more could you get with tricky logic?
> I agree that modern tools and parts have allowed a lot more people to build 
> digital circuits.
> -- 
> These are my opinions.  I hate spam.
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