[time-nuts] Using CPLD/FPGA or similar for frequency

Hal Murray hmurray at megapathdsl.net
Wed Jun 10 03:28:15 EDT 2015

alan.ambrose at anagram.net said:
> How about a 1pS resolution TIC? :)

An alternative way to describe that sort of problem is
  How accurately can you locate an edge?

I haven't looked carefully at the Spartan 3E.  You might be able to run a 
signal along a column through a slow path and clock the whole column at the 
same time.  Then sort out how far it got.  That "slow path" is basically a 
delay line with many taps.

It would take some experimentation, and maybe some duplicate logic for run 
time calibration.

> Or a >12 digit frequency counter? :) :)

12 digits is easy.  Just wait long enough.

So that turns into 2 games:
  How fast can you count?
  How many digits can you get in 1 second?

Here is a toy that would be useful:
  assume you have a 10 MHz reference clock.
  make a design that captures something like a PPS and spits out the 
time-stamp on a serial port.  I think Tom has a PIC that does that.  The idea 
here is to use a faster clock so you get better resolution.  How much 
resolution can you get with pure digital logic?  (no delay lines)

I'd like something like that watching the power line.  You might need some 
sort of compression scheme or the serial port would get overloaded.   9600 
baud is 1K characters per second.  60 Hz is 16 ms per cycle so you get 15 
characters per cycle (plus a separator) unless there is noise on the line.  9 
digits gives you ns. within the second.  Every second or so you could send 
the high-order digits.

These are my opinions.  I hate spam.

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