[time-nuts] Using CPLD/FPGA or similar for frequency

Bob Camp kb8tq at n1k.org
Fri Jun 12 08:43:59 EDT 2015


Hi

Well, take the CPLD up to 100 MHz, and feed 20 ns pulses to the TDC’s RC, drive that into a cheap 24 bit sigma delta A/D and you have an easy 1 Fs. Do a little processing on multiple samples and you have 15 displayed digits.

=====

Of course everything past about 50 ps is just noise ….

It all depends on what you are after:

Resolution
Accuracy
Repeatability 

The first one is easy in any system. The last one can fool you. The one in the middle is what you actually were after in most cases. 

Bob

> On Jun 11, 2015, at 10:22 AM, Alan Ambrose <alan.ambrose at anagram.net> wrote:
> 
> Hi,
> 
>>>> 
> So that turns into 2 games:
>  How fast can you count?
>  How many digits can you get in 1 second?
> <<<
> 
> A clever interpolator for frequency or TIC would kill it - for TIC essentially a PICTIC on steroids. The PICTIC does 19pS with a 10 bit ADC and a 66MHz clock, an SR620 does 4pS with a 12 bit ADC and an 80 MHz clock - so ... cough ... Spartan 3E at 256MHz with 16 bit ADC - and 1pS should be easy
> 
> Alan
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