[time-nuts] Using CPLD/FPGA or similar for frequency
attila at kinali.ch
Mon Jun 15 18:03:16 EDT 2015
On Wed, 10 Jun 2015 21:45:33 -0400
Bob Camp <kb8tq at n1k.org> wrote:
> The delay line in an FPGA approach might get you to 20 ps. There is a lot of hand
> waving in the calibration process to get there. ( = figuring out that state A came before
> state B is based on things that are difficult to prove).
> If you do get it calibrated, you then find that it’s sensitive to both supply voltage and
> to temperature. The supply thing you can take care of with a good regulator. The “shifts
> all over the place when you put your thumb on it” T/C is not quite as easy to deal with.
> A TDC using an R/C and an ADC is a *much* easier way to go.
Just two references on this topic:
 Is AFAIK the only way to get FPGAs below the intrinsic cell delay
(which is varies between a min of 10-20ps and a max of 100-200ps within
the same FPGA)
And  gives an idea how a possible calibration system might work.
 "The 10-ps wave union TDC: Improving FPGA TDC resolution beyond its
cell delay", by Wu, Jinyuan and Shi, Zonghan, 2008
 "Statistical Linearity Calibration of Time-To-Digital Converters Using
a Free-Running Ring Oscillator", by Rivior, 2006
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