[time-nuts] Using CPLD/FPGA or similar for frequency

Alan Ambrose alan.ambrose at anagram.net
Wed Jun 17 13:46:37 EDT 2015

In my mind, at least, this is still the same subject…

Does anyone have any results to share re the SiLabs Si53xx ‘Jitter Attenuating Clock Multipliers​’?

Is this a helpful way to supply a 1GHz counter with a ‘0.1ps rms phase jitter’ clock?


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