[time-nuts] Looking for ECL divide by 3 with symmetry

ed breya eb at telight.com
Sat Oct 3 12:33:27 EDT 2015

After studying the various divide by 3 circuits, I decided to try 
designing one that would be simpler in terms of package count, using 
available ECL DIPs on-hand. Instead of the JK-FF version followed by 
duty cycle-fixing circuitry, I opted for two 10131 dual D-FFs to provide 
the state machine, with 50 percent duty cycle. A 10116 line receiver 
provides the input interface and two-phase clock. So, a circuit of three 
DIP packages does the whole works.

A quick paper analysis showed that it should work. I gathered up the 
parts and I built it onto a small vector circuit board, but it did not 
work. I did it relatively quickly, so probably have a wiring error to 
figure out. To make sure I didn't miss something, I ran a check with a 
simple logic simulator that I found, and it proved out OK, design-wise, 
so I think it should be good to go once I figure out the proper wiring.

A summary of the circuit and operational simulation is attached. It 
should be fully synchronous and glitchless up to the toggle limit. Also, 
starting it from the one disallowed state seems to be no problem - it 
quickly cycles to the proper sequence. Using D-FF decoding within the 
counter section has a little more prop delay than the gated versions. I 
didn't check the timing limitations yet, but I'm pretty sure it will be 
OK at the required 50 MHz toggle rate.

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