[time-nuts] Digital Phasae Lock Loops

Magnus Danielson magnus at rubidium.dyndns.org
Sat Oct 17 17:13:17 EDT 2015


On 10/17/2015 01:57 PM, Tom Van Baak wrote:
> Martyn Smith wrote:
>> All we want to do is lock a 10 MHz ULN OXCO to a rubidium.
>> So basically a clean up loop.
>> Then we can provide an ULN output from the ULN OXCO and long term stability from the rubidium.
>> The 10 MHz ULN OXCO has phase noise of –115 to -120 dBc/Hz @ 1 Hz with a –174 dBc noise floor.
>> The rubidium’s phase noise at 1 Hz is about –105 dBc.
>> So for the PLL to remove the poor rubidium phase noise I need a loop BW of less than 0.2 Hz.
>> I have tried digital PLL’s from other companies.  One you can specify the bandwidth down to 1 mHz.
>> But they are very unreliable, subject to flicking out of lock now and then.
>> At the moment we use an analog PLL with a loop bandwidth around 0.2 Hz.
>> That works well for my ULN OXCO’s that make about –113 dBc at 1 Hz.
>> But now we are getting even lower phase noise at 1 Hz (-115 dBc and below), I need
>>     a smaller loop BW, and we aren’t able to get that with an analog PLL.
> Ok, thanks for the clarification. I'll leave it up to those with more experience to recommend a solution. I'd be surprised if using a digital PLL helps here. Are you sure you've reached the limit of what you can do with analog?

First of all, digital PLLs is an overloaded term. I consider many of the 
PLLs I do digital, but they are DSP based with software, but essentially 
just normal PI-loops. The benefit of doing a PI-loop in digital is that 
the integrator does not have loss in the same way that the analog 
integrator does, which helps with bandwidths below 1 Hz.
What is fairly critical is to maintain fairly high resolution on the 
input and output, but definitively in the integrator. However, in the 
DSP-side, maintaining many bits in the integrator is so cheap, that it 
stupid not to do it.

> BTW, if your existing clean up oscillator is "very unreliable" consider that it may be your oscillator and not the PLL. For this you do not want to use ADEV or L(f) statistics. A one-time phase jump can cause loss of lock and averaging statistics will not tell you this. Instead you may want to look at the raw phase data and quantify the jumps. Occasional large jumps may not show up at all in an ADEV plot but can cause trouble for a PLL. Magnus, would MTIE be appropriate here?

Great question.

MTIE could indeed be useful, but it one has to understand what MTIE 
means, so it can be a bit confusing initially. MTIE is however the 
telecom sync guys way of expressing long term systematic noise and is a 
mirror-version of the sine-jitter tolerance test which is so helpful.

I often look at phase and frequency raw-data. MTIE is a process-variant 
of the phase-data to illustrate the maxiumum difference between min and 
max value of a sweeping window of size tau. MTIE and sine 
jitter-tolerance curves are very handy as they illustrate the 
peak-to-peak systematics for different frequencies/time which then 
convert to buffer sizes and PLL bandwidths.

Cycle-slipping is a good search-term. When cycle slipping occurs, you 
usually get a high spike in the frequency plane, so they are usually 
easy to spot there, and then go for the phase plane to see how the 
transition looked. TimeLab is hell of a good tool to fool around with 
such things.


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