[time-nuts] Unified VCXO Carrier Board

Gerhard Hoffmann dk4xp at arcor.de
Thu Oct 22 03:40:59 EDT 2015

I'd like to design a unified VCXO Carrier Board to these requirements:

1. It can host one of the the following VCXOs:

1.1. HP 10811A-6111 (as from 5370A)

1.2 Morion MV89A

1.3 MTI 260

1.4 CV-950

1.5 Timetech

1.6 Axtal

1.7 Pascall

2. It provides unified tuning: 0V = lowest possible frequency, 3V3 or 5V 
= highest possible frequency, no matter of the VCXO tuning sense and range.

3. provides a 5V tuning voltage reference for those VCXOs that don't 
have one of their own.

4. Frequency can be adjusted from external Vtune input and from a 10 
turn pot.

5.Board has 2 reference frequency inputs with LTC6957 receivers. One of 
them can interface the onboard VCXO to the CPLD.

6. Board has a 1pps input 3V3 CMOS level

7. It can lock the VCXO to the reference frequency or the 1pps in. 
Provides LED lock indication.

8. It features a Xilinx Coolrunner2 2C64 CPLD, complexity 64 FlipFlops + 
combin. Logic. Unused Pins are brought out to Testpoints in 100 mil 
grid. The Coolrunner remembers its configuration and can be reprogrammed 
using the standard Xilinx USB dongle. It has a 10 pin 2mm header for 
this purpose. Small circuits can run at 200 MHz. This function exists 

9. The Coolrunner provides a standard 1pps /20us out, maybe 10/100/1000 pps.

10. 2 Monoflops for 1pps LEDs in/out

11. There are 2 output buffers that drive valid 3V3 CMOS into 50 Ohms. 
They can be re-clocked to LTC6957 outputs with 1G74 flipflops.

12. Unbuffered VCXO output is available on SMA connector

13. One additional buffered output (LMH6702/AD8009 or discrete to avoid 
neg. supply). This is not meant to be a distribution amplifier.

14. Regulators for the voltages needed.

15. Requires soldering skills 0603 / sot23-5 / MSOP. No commercial 
interest. Could be TAPR or DIY.

I'm open to suggestions & ideas.

Gerhard, DK4XP

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