[time-nuts] Unified VCXO Carrier Board

David C. Partridge david.partridge at perdrix.co.uk
Sun Oct 25 09:23:13 EDT 2015


I wish that people had said that the ADCMP600 was a mediocre comparator when I designed the board - I’d have used a better one!

I can't find the post about the design and die level issues in a quick search (I've been off line for a few weeks).


I couldn't find your post about your measurements of my board for the same reason.

David Partridge 
-----Original Message-----
From: time-nuts [mailto:time-nuts-bounces at febo.com] On Behalf Of Charles Steinmetz
Sent: 24 October 2015 14:03
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Unified VCXO Carrier Board

Bruce wrote:

>The comparator circuit measured was the front end of David Partridge's 
>divider. I merely measured the 10MHz output.

The MAX999 and ADCMP600 are the two comparator options noted on David's schematic.  Both parts suffer from a number of the design and die-level issues I noted in my previous message, and I have never obtained particularly good PN with either one.  Also, even the relatively direct path to the 10MHz output goes through two 'AC04 inverters and an 'AC541 line driver, which contribute additional PN.

>One thing that I have found is that at low offset frequencies the 
>measured PN is substantially reduced when air currents and other 
>sources of thermal fluctuations are reduced. Even the effect of a thin 
>piece of paper used as an air current shield can be easily seen.
>With careful shielding from thermal fluctuations I measure the low 
>frequency offset PN to be substantially lower than the datasheet values.
>I've seen this effect with everything for which I've measured the PN.

Agreed.  Whether or not it is explicitly stated, I take "all circuitry to be enclosed and protected from drafts, and allowed to stabilize thermally before testing" as a given with any sensitive time or voltage circuit.

>One problem with comparators when attempting to measure their PN is 
>that they don't have sufficient output to drive the TimePod input directly.
>An amplifier is required.

The spec sheet says both TimePod inputs accept -5 to +20dBm into 50 ohms.  -5dBm is less than 0.4Vp-p, which requires less than +/-4mA from the source, so a 0-5v comparator output feeding a coupling capacitor and a 560 ohm series resistor should work fine as long as the comparator can source and sink at least 4mA.

Alternatively, a 0-5v comparator output could be buffered with three
'AC04 inverters in parallel, or an 'AC line driver -- but that adds the PN of the gates.

>A resistor from point A to ground in the Wenzel style shaper you 
>attached has little effect on the output symmetry due to C4.

It has just enough effect to correct the very small (<1%) asymmetry due to the unbalanced drive.  (With no resistor at Point A, the duty cycle is ~51%/49% high/low.)

>However it does allow the output amplitude to be adjusted.

According to the simulation, the resistor has no effect on the output amplitude until it is well below 1k ohms (at 1k ohm, the symmetry has been WAY overcompensated and the duty cycle is ~45%/55% high/low.

Best regards,


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