[time-nuts] Advise on building a DIY GPSDO?

[Magnus Danielson]

Lars and Charles,

On 04/28/2016 05:27 AM, Charles Steinmetz wrote:
> Lars wrote:
>
>> Could you please explain a little more about this:
>>      *     *     *
>> What is the systematic ripple?
>> Is the comparison frequency normally 1Hz (1PPS)?
>> What is the algorithms used?
>> If I sample the difference between the PPS and the divided 10MHz
>> output every second and have a third order loop driving a DAC will I
>> get systematic errors?
>
> Ummmmm -- please do not take this the wrong way, but you seem to be
> asking for short-cuts and cookbook solutions to very complex design
> issues in advanced PLL design, apparently without having a good
> understanding of the basics of PLL design (as indicated by your
> questions: what is the comparison frequency, what is systematic ripple,
> etc.).
>
> That is just not the way it works.  System designs are organic --
> everything affects everything else.  One needs a comprehensive
> understanding of the whole subject to deal with all of the consequences
> of each contemplated design choice.  There are just too many degrees of
> freedom in a design at that level of complexity and performance to make
> short-cuts and cookbook solutions possible.
>
> Most anyone can throw together a first-order PLL using cookbook
> solutions and make it basically work (i.e., the loop doesn't oscillate
> and it converges to lock).  But this doesn't even begin to make a decent
> GPSDO design.  Not only must the loop converge and not oscillate, the
> loop tuning must match the OCXO being used, it must hold errors down to
> PPT levels and below, and it must address errors at the second, third,
> and higher levels of analysis.  There is just no easy, or formulaic way
> to incorporate results of the required, interdependent analyses without
> actually performing those analyses.  There are no short-cuts.
>
> Here is a post from October on the same subject:
>
>       <https://www.febo.com/pipermail/time-nuts/2015-October/094472.html>
>
> And here are links to the best PLL design texts I'm aware of:
>
>       Gardner:  <http://www.amazon.com/dp/0471430633>
>       Best:  <http://www.amazon.com/dp/0071493751>
>       Egan 1:  <http://www.amazon.com/dp/0470118008>
>       Egan 2:  <http://www.amazon.com/dp/0470915668>
>       Stephens:  <http://www.amazon.com/dp/0792376021>
>       Wolaver:  <http://www.amazon.com/dp/0136627439/>
>
> I suggest that you get all of these books (or, at minimum, three of
> them, after reviewing the tables of content and some relevant pages
> using Google Books or "look inside" on Amazon) and study them -- really
> study them.  (I'm betting that if you study any three of them, you will
> end up getting the other three and probably other books as well.)  In
> time, you will be able to answer the questions you are asking, and to
> pose the next several hundred questions you will need to answer to
> design a well-optimized GPSDO.

I have found that I use Gardner, Best and Wolaver together. They 
complement each other in a nice fashion.

Gardner is the authoritative text, and reading it carefully gives a 
qualitative understanding.

Best is maybe somewhat more easier to get to, but also have some 
approaches that sometimes complements the Gardner.

The Wolaver book is really a very nice complement to the Gardner, it 
provides a very smooth reading but also more variations of circuits and 
some analysis which isn't in the other books that can be really helpful.

If you want to learn and extend in the field, I would not go without the 
Gardner and Wolaver. There might be other books covering what Best covers.

I have additional books, but these is what I find that I use for PLLs.
There is also the "Jitter in Digital Transmission Systems" which can 
provide additional insights that the others lack.

Cheers,
Magnus