[time-nuts] MV89A / MTI-260 / HP10811 carrier board
Bob Camp
kb8tq at n1k.org
Sat Feb 27 10:15:55 EST 2016
Hi
You will run into the same problem on the Altera side. Their “super suite” is called Quartus and
the latest free version only supports the newer parts. Once you get a few generations back, you
need to download an older version. That’s not impossible to do or crazy to work with. The newer
stuff is a bit better. The generation to generation transitions are not insane, but they will take up
time working this and that out. Much better (if possible) to start with a part that the current software
just started supporting. In the Altera case that is the Max10 family. The lowest cost member is
less than $4 in single piece quantity on Mouser. Yes it’s a BGA. The leaded parts are about $11 or so.
Demo boards with various cool things on them are < $40.
Yes this sounds like an advertisement for Altera. It’s not really. All of the same basic issues apply equally
to the other vendors. It’s a competitive world and they all do a pretty fast game of catch up. The only unique
feature (AFIK) with Quartus is the inclusion of schematic entry. It lets you do a “no code” design if you are
more familiar with logic schematics than with VHDL. If any of the “other guys” do this, it would be worth knowing
about in the context of many of the people on the list being a bit code shy.
Bob
> On Feb 27, 2016, at 3:03 AM, Bruce Griffiths <bruce.griffiths at xtra.co.nz> wrote:
>
> To program the chip one needs a USB to JTAG programming cable and development software to produce the programming data file for the chip.
> The Xilinx Coolrunner II CPLDS are only supported by Xilinx's ISE software which is obsolete. Vivado the current development software doesn't support them.
> Bruce
>
>
> On Saturday, 27 February 2016 12:01 PM, Tom Van Baak <tvb at LeapSecond.com> wrote:
>
>
> Gerhard Hoffmann wrote:
>> I have never used PICs and given their life cycle it's a bad time to jump on the train.
>> Not now when I'm just converting everything to ARM.
>
> Hi Gerhard,
>
> The 12F-series that I use for the PIC dividers is very solid. These are sold by the billions. Not sure what train you're talking about. Don't confuse ARM and x86 chips du jour with something like an 8-pin 8-bit PIC. For more info on the PIC dividers see:
> http://leapsecond.com/pic/picdiv.htm
> http://leapsecond.com/pic/picdiv-list.htm
>
> Thanks for posting the sample Xilinx code. That's intriguing. So if I started from scratch, what does it take to turn your firmware source code into a working chip? Are any of the chips as small or as cheap as a SMT or DIP PIC?
>
> By contrast, the (pd10.asm) PIC code to generate a 10 ms wide 1PPS from 10 MHz is two macros and a loop:
>
> DELAY_24996 MACRO ; delay 24996 instructions
> movlw d'249'
> call DelayW100
> movlw d'94'
> call DelayW1
> ENDM
>
> DELAY_2474996 MACRO ; delay 2474996 instructions
> movlw d'247'
> call DelayW10k
> movlw d'49'
> call DelayW100
> movlw d'93'
> call DelayW1
> ENDM
>
> ; Set output pins high for 10 ms = 25,000 Tcy at 10 MHz.
> rise: movlw 0xFF
> movwf GPIO
> DELAY_24996
> goto fall
>
> ; Set output pins low for 990 ms = 2,475,000 Tcy at 10 MHz.
> fall: movlw 0x00
> movwf GPIO
> DELAY_2474996
> goto rise
>
> /tvb
>
> ----- Original Message -----
> From: "Gerhard Hoffmann" <dk4xp at arcor.de>
> To: <time-nuts at febo.com>
> Sent: Thursday, February 25, 2016 5:30 PM
> Subject: Re: [time-nuts] MV89A / MTI-260 / HP10811 carrier board
>
>
>> Am 25.02.2016 um 22:23 schrieb Magnus Danielson:
>>> Interesting. I would consider the PICDIV such as that of TADD-2, which
>>> has the benefit of producing a range of frequencies, so that a
>>> suitable can be selected as matching the needs. I've found it very
>>> useful property of the TADD-2, where I have my TADD-2s wired up to
>>> output one of each. I also wired them to output the buffered variant
>>> of the clock, which gives better measures compared to running the sine
>>> straight into the counters.
>>
>> I have never used PICs and given their life cycle it's a bad time to
>> jump on the train.
>> Not now when I'm just converting everything to ARM. OTOH I have used
>> Xilinx since they exist
>> and this board is more or less a cleanup of things that are already there..
>>
>>
>> This here is all it takes for 10 and 100 MHz oscillators:
>>
>> ----------------------------------------------------------------------------------
>> -- Company: Hoffmann RF & DSP
>> -- Create Date: 09:09:37 08/08/2012
>> -- Module Name: pps1_generator - Behavioral
>> -- Target Devices: X2c64A-5VQ44
>> -- Additional Comments: Free firmware under BSD license
>> ----------------------------------------------------------------------------------
>> library IEEE;
>> use IEEE.STD_LOGIC_1164.ALL;
>> use ieee.numeric_std.all;
>>
>> entity pps1_generator is
>> Port(
>> clk : in STD_LOGIC;
>> RunAt100MHz : in STD_LOGIC;
>> pps1_out : out STD_LOGIC;
>> );
>> end pps1_generator;
>>
>> architecture Behavioral of pps1_generator is
>> signal tctr : integer range 0 to 99999999;
>> signal pw_ctr : integer range 0 to 199999;
>> signal cycle_done : boolean;
>> signal pw_done : boolean;
>>
>> function bool2sl(b : boolean) return std_logic is
>> begin
>> if b then return '1'; else return '0'; end if;
>> end function bool2sl;
>>
>> begin
>>
>> u_div : process(clk) is
>> begin
>> if rising_edge(clk) then
>> cycle_done <= (tctr = 0); -- pipeline the comparator
>>
>> if cycle_done
>> then
>> if RunAt100MHz = '1' then
>> tctr <= 100000000 - 2; -- divide by 100 Meg
>> else
>> tctr <= 10000000 - 2; -- divide by 10 Meg
>> end if;
>>
>> else
>> tctr <= tctr - 1;
>> end if;
>>
>> end if; -- rising_edge()
>> end process u_div;
>>
>>
>> -- produce the standard 20 usec pulsewidth
>> u_pulsewidth : process(clk) is
>> begin
>> if rising_edge(clk) then
>> if cycle_done then
>> if RunAt100MHz = '1' then
>> pw_ctr <= 19999;
>> else
>> pw_ctr <= 1999;
>> end if;
>>
>> elsif pw_ctr /= 0 then
>> pw_ctr <= pw_ctr - 1;
>> end if;
>>
>> pps1_out <= bool2sl(pw_ctr /= 0);
>>
>> end if; -- rising_edge()
>> end process u_pulsewidth;
>>
>> end Behavioral;
>> -------------------------------------------------------------------------------------------------------------
>>
>>
>>
>> I have also a version that fits into 2 chips, runs at Osc = 200 MHz and
>> produces a fixed 1/10/100/1000pps and another pps that can be shifted
>> against the first one in 5nsec steps over > 1 second.
>> It also provides control for a Micrel ECL chip that does the ps
>> interpolation
>> between the 5 ns steps.
>>
>> It has a shift register interface that is controlled by a Beagle Bone Black
>> under Debian Linux, so network access is free.
>>
>> Ideal for testing ranging systems and TICs / TDCs, but it still needs
>> some software.
>>
>>>
>>> The power-supply input didn't look all that clear. It would be handy
>>> if a single input could be used.
>>>
>> It can run on -5...-8V (for the opamps) and +12V for Morion and MTI;
>> the HP10811 needs 20V or so
>> for its heater. In this case the 12V is made from the 20V. I do not want
>> a switcher there.
>>
>>
>>
>>> I could probably have use for several of these boards.
>>>
>> Me too. I have recently decremented the number of available Lucent REF 0
>> plug-ins quite substantially.
>>
>> (BTW: The Lucent REF 1 units with GPS are completely sold out for good,
>> I have asked.)
>>
>> The idea is to lock 8 or 16 5 MHz MTI-260s to something long-time
>> stable and see
>> how far I get wrt phase noise when I combine the outputs.
>>
>> Seems to be more promising than that promiscuous coupled resonator stuff
>> that was promoted recently. It is even somewhat tunable.
>>
>> I like throwing repetitive hardware at problems when I get sth. in return..
>> Like my 220pv/sqrtHz preamp with 20 low noise opamps averaged.
>>
>> regards, Gerhard, DK4XP
>>
>>
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