[time-nuts] GPS message jitter (was GPS for Nixie Clock)

jimlux jimlux at earthlink.net
Mon Jul 18 17:17:24 EDT 2016


On 7/18/16 12:35 PM, David wrote:
> On Mon, 18 Jul 2016 11:43:32 -0700, you wrote:
>
>> except that virtually every UART in use today has some sort of buffering
>> (whether a FIFO or double buffering) between the CPU interface and the
>> bits on the wire, which completely desynchronizes the bits on the wire
>>from the CPU interface.
>>
>> Determinism in UART timing between the CPU bus interface and the "bits
>> on the wire" has never been something that is specified.  You can go
>> back to venerable parts like the 8251, and there's no spec in the data
>> sheet.
>> ( there's a tCR specified as 16 tCY for the read setup time from CTS*,
>> DSR* to READ* assert.  And tSRX (2 usec min) and tHRX (2 usec min) for
>> the setup and hold of the internal sampling pulse relative to RxD. And
>> 20 tCY as a max from center of stop bit to RxRDY, and then whatever the
>> delay is from the internal RxRDY to the bus read)
>
> Long ago I remember seeing a circuit design or application note using
> an 8250 or similar where the UART start bit was gated so that the
> leading edge could be used for precision synchronization.

And it probably depended on idiosyncratic behavior of the 8250 and 
fooling with the transmit clock input to the chip.   That is, a part 
that claimed "8250 emulation" may or may not work the same.  Sort of 
like Printer ports on IBM PCs.. they'd all work with a unidirectional 
Centronics printer, some would work as a bidirectional port, some wouldn't.

As soon as you get to parts that have the baudrate generator internally 
or which are highly integrated multiprotocol chips (like the Zilog do 
everything dual serial port) it gets much trickier.

I had a terrible time a couple years ago getting a synchronous RS422 
interface (1 pair with clock at symbol rate + 1 pair with data) that 
would easily interface to a PC.  Most of the "synchronous RS422" 
interfaces out there use one of the multiprotocol chips which support 
BiSync, HDLC, etc. and they try to find sync characters or stuff flags, 
etc. but not very many support "raw synchronous"











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