[time-nuts] Commercial software defined radio for clock metrology

[Michael Wouters]

The following may be of interest to those playing with low-cost SDR hardware:

I also have been looking at low-cost SDR hardware for T&F measurements
and have made an RF phase meter based on the Red Pitaya. The
performance of this was not as good as I was hoping for: the
fractional frequency resolution of this is about 10E-12 at 1 second
averaging time. An earlier implementation on fairly ordinary NI
hardware (14 bit 100 MHz ADCs) did better than 10E-13. Part of the
problem seems to be that although the RP ADC is 14 bits, the effective
number of bits is really only 10, according to a study I read (ENOB
for the NI ADCs is specified as 12). The RP is a bit constrained for
DSP resources too - it was a struggle to squeeze in the decimation
filters.

Cheers
Michael

On Sat, May 28, 2016 at 10:17 AM, Bruce Griffiths
<bruce.griffiths at xtra.co.nz> wrote:
> On Thursday, May 26, 2016 06:40:26 PM Bob Camp wrote:
>> Hi
>>
>> Very interesting paper, thanks for sharing !!
>>
>> One question:
>>
>> In many DMTD (and single mixer) systems, a lowpass and high pass filter are
>> applied to the signal coming out of the mixer. This is done to improve the
>> zero crossing detection. It also effectively reduces the “pre detection”
>> bandwidth. My understanding of the setup in your paper does not do this
>> sort of filtering. It simply operated directly on the downconverter signal.
>>  Is this correct? I may have missed something really obvious in a quick
>> read of the paper…..
>>
>> Thanks!
>>
>> Bob
>
> All the filtering and down mixing is done in the digital domain.
> Anitialiasing filters in front of the ADCs are also be required.
>
> A 2  (or more) receive channel SDR board would be a nice tool to use for this
> provided the FPGA is large enough.
>
> Bruce
>
>>
>> > On May 25, 2016, at 12:01 PM, Sherman, Jeffrey A. (Fed)
>> > <jeff.sherman at nist.gov> wrote:
>> >
>> > Hello,
>> >
>> > A recently published paper might be of interest to the time-nuts
>> > community. We studied how well an unmodified commercial software defined
>> > radio (SDR) device/firmware could serve in comparing high-performance
>> > oscillators and atomic clocks. Though we chose to study the USRP
>> > platform, the discussion easily generalizes to many other SDRs.
>> >
>> > I understand that for one month, the journal allows for free electronic
>> > downloads of the manuscript at:
>> > http://scitation.aip.org/content/aip/journal/rsi/87/5/10.1063/1.4950898
>> > (Review of Scientific Instruments 87, 054711 (2016))
>> >
>> > Afterwards, a preprint will remain available at:
>> > http://arxiv.org/abs/1605.03505
>> >
>> > There are commercial instruments available with SDR architecture
>> > under-the-hood, but they often cost many thousands of dollars per
>> > measurement channel. In contrast, commercial general-purpose SDRs scale
>> > horizontally and can cost <= $1k per channel. Unlike the classic
>> > dual-mixer time-difference (DMTD) approach, SDRs are frequency agile. The
>> > carrier-acceptance range is limited not by the sample clock rate but by
>> > the ADC's input bandwidth (assuming one allows for aliasing), which can
>> > be many times greater. This property is an important feature in
>> > considering the future measurement of optical clocks, often accomplished
>> > through a heterodyne beatnote (often at "practically any" frequency
>> > between ~1 MHz to 500 MHz) with a femtosecond laser frequency comb. At
>> > typical microwave clock frequencies (5 MHz, 10 MHz), we show that a stock
>> > SDR outperforms a purpose-built DMTD instrument.
>> >
>> > Perhaps the biggest worry about the SDR approach is that fast ADCs are in
>> > general much noisier than the analog processing components in DMTD.
>> > However, quantization noise is at least amenable to averaging. As you all
>> > likely appreciate, what really limits high precision clock comparison is
>> > instrument stability. In this regard, the SDR's digital signal processing
>> > steps (frequency translation, sample rate decimation, and low-pass
>> > filtering) are at least perfectly stable and can be made sufficiently
>> > accurate.
>> >
>> > We found that in the studied units the limiting non-stationary noise
>> > source was likely the aperture jitter of the ADC (the instability of the
>> > delay between an idealized sample trigger and actuation of the
>> > sample/hold circuitry). However, the ADC's aperture jitter appears highly
>> > common-mode in chips with a second "simultaneously-sampled" input
>> > channel, allowing for an order-of-magnitue improvement after
>> > channel-to-channel subtraction. For example, at 5 MHz, the SDR showed a
>> > time deviation floor of ~20 fs after just 10 ms of averaging; the
>> > aperture jitter specification was 150 fs. We also describe tests with
>> > maser signals lasting several days.
>> >
>> > Best wishes,
>> > Jeff Sherman, Ph.D.
>> > --------------------------------------------------------------------
>> > National Institute of Standards & Technology
>> > Time and Frequency Division (688)
>> > 325 Broadway / Boulder, CO 80305 / 303-497-3511
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