[time-nuts] 1PPS to 32.768 khz

[Robert LaJeunesse]

One needs to be careful when generating the 32.768KHz signal. If it's used to clock a PLL internal to the clock's microcontroller then providing a the right pulse count, at the wrong frequency and interrupted, could result in poor or no clock operation. If it drives the display multiplexing there could be unpleasant "breathing" of the display intensity. If it just drives a counter, no big concern. 

(Me, I'd consider a small microcontroller that's crystal clocked at 8.388 MHz and divided down by 128 (+/-1 or 0) to create the required output edge. Also divide that by 256*256 to create a signal that gets compared to the 1 Hz reference. Based on the comparison adjust the (+/-1 or 0) for the next half cycle as need be to phase lock.)

Bob LaJeunesse

> Sent: Wednesday, October 19, 2016 at 7:15 PM
> From: "Mark Sims" <holrum at hotmail.com>
> To: "time-nuts at febo.com" <time-nuts at febo.com>
> Subject: [time-nuts] 1PPS to 32.768 khz
>
> Here's another way to do it for a wall clock display...   set up an oscillator/divider (or even a 555 timer) to generate a frequency close to, but faster than 65536 Hz.    Setup a 16 bit counter clocked by that signal. When the 1PPS signal arrives, start the counter.  After 65536 pulses the counter will overflow... stop the counter (and set up for the next 1PPS trigger) when that happens.   The Q0 output (lowest bit) from the counter will be a burst of 32768 pulses that repeats once a second.  Use that to drive your clock.   The slight pause between bursts of 32768 pulses will not be noticed on the clock display.