[time-nuts] Sub-ps delay line

[ed breya]

If you make a variable delay by adding external RC (varicap) circuits, 
the edges will be slower, and the amplitudes will be affected. This will 
tend to complicate the detection and reshaping of the clock by the 
LTC6957. Pay particular attention to page 24 and Fig 8 in the datasheet, 
regarding the strong effect of input overdrive on prop delay and 
symmetry. This should be considered in the design of anything added in 
front.

It may be better to use this effect advantageously instead, to get 
variable delay by tweaking DC bias in the right places. Depending on 
which edges are ultimately used in the ADCs and DACs, you may be able to 
affect all sorts of beneficial timing control - or have all sorts of 
timing problems - depending on how you handle it.

Ed