[time-nuts] Sub-ps delay line
ch at murgatroid.com
Thu Feb 9 01:24:06 EST 2017
is it possible to run each ADC using whatever phase of the common clock you
have, measure the local phase differences between ADC's periodically, and
then work out the necessary sample offsets for the ensemble in software?
this ought to be more robust than trying to hold everything fixed over long
time and wide temperature. (you'd still want to minimize excursions, of
73 de AI6KG
On Wed, Feb 8, 2017 at 3:25 AM, Mattia Rizzi <mattia.rizzi at gmail.com> wrote:
> thank you all for the answers!
> The description I gave in the first email is a simplification of the
> system. The delay line is used to phase-match the clocks of a distributed
> measurement system. Each board feature an ADC and a DAC. You can see it as
> a distributed RF acquisition system, with microwave requirements on phase
> matching. The delay line is used ALSO to correctly align the clocks for the
> ADCs, since each IC has an unknown Aperture Delay (PVT kicks in).
> Unfortunately I cannot change the voltage references to introduces a
> variable delay. That's also why I would like to have a delay line rather
> than a set-and-forget solution: I can compensate for PVT of the ADC and DAC
> as well.
> About temperature variation: LTC6957-1 is excellent, 0.1ps/C of propagation
> delay change. I still have to check with Linear if this figure is valid
> also if you don't use BOTH (P and N) output clock lines. I'm not sure to
> use a balun (such as Minicircuit ADT2-1) for differential-to-single-ended
> conversion because I dont want to introduce additional tempco.
> Unfortunately, Mini-circuit has no data about that. The varactor itself has
> a slight tempco, but the overall tempco should be below 1 ps/C.
> About voltage & supply variations: I'm planning to use a dedicate LDO for
> the delay line. LTC6957-1 has a maximum of 50ps/V propagation delay
> variation, I'm expecting to use an LDO with <1 mV/C of regulation
> stability (LT3045 has less than 100uV over 20 degree variation, but it's a
> bit expensive). Again, I don't know if the 50ps/V figure is still valid
> using only one output, but since LVPECL output stages are done using a BJT
> always in the active region, I'm expecting an isolation from the power
> supply voltage.
> >My first thought would be to use a pair of couplers before and after the
> delay line and bring it into a mixer to serve as a phase detector such that
> you can create a control loop to stabilize delay. This way you get a handle
> on the temperature variations.
> Thanks! Do you know a phase detector with such requirements on stability? I
> checked Mini-circuit but they don't have factory data on the stability of
> their products. Also, my signals are clocks rather than pure sinewaves.
> >I would also advise you take a look at how well you can maintain your
> system impedance, say 50 Ohms. For example, I have seen about 100's ps
> phase difference on a 10 MHz reference, using one BNC female-female coupler
> versus another
> Yes, this is a calibration issue (repeatability) to be investigated, but
> since microwave systems have the same issues I hope there's already a way
> to how achieve that.
> Thank you!
> 2017-02-07 23:43 GMT+01:00 Magnus Danielson <magnus at rubidium.dyndns.org>:
> > Hi,
> > My first thought would be to use a pair of couplers before and after the
> > delay line and bring it into a mixer to serve as a phase detector such
> > you can create a control loop to stabilize delay. This way you get a
> > on the temperature variations.
> > There is trombone delays that can be used. They seem to reach that level
> > of resolution.
> > There is microstepper boxes, but usually they operate on 5 or 10 MHz.
> > There is multiple ways to design delays for CW signals, microsteppers
> > various forms of gear-boxes and programmable generators. Chips either use
> > gate delays or programmable comparator vs. ramp of some form.
> > Ensuring temperature stability and drift limits is however always an
> > Delay loop oscillator for calibration can be done, but biases can be
> > problematic, so a number of different setups needs to be done to build
> > confidence. It's a combinatorial exercise which is quite interesting.
> > Cheers,
> > Magnus
> > On 02/07/2017 05:13 PM, Mattia Rizzi wrote:
> >> Hello,
> >> I'm looking/designing a sub-ps delay line with very high stability.
> >> Basically it has microwave requirements on phase matching.
> >> The main features that such delay line should have are:
> >> - sub-ps resolution and about 1 ns range
> >> - High stability, must not drift more than 2ps/year, preferably 1ps/year
> >> - Temperature coefficient (tempco) below 1 ps/celsius
> >> - Low phase noise floor, target random jitter below 100 fs RSM from
> >> to 1MHz.
> >> - flicker noise below -90dBc at 1Hz (100MHz carrier)
> >> - cheap (below 50 euros) and PCB integrable
> >> - optional: autocalibration or a way to check calibration health over
> >> (checking the oscillation frequency of the delay line connected as
> >> Operating conditions: The delay line will be used for RF distribution,
> >> where the clock signals (100-200MHz) must stay in +/- 10 ps error
> >> Since timing jitter (wander) is 1.6ps RMS, the delay line must be very
> >> accurate, with maximum of +/- 3ps of delay uncertainty. The delay line
> >> used to phase-match the clock outputs at factory, hence will not be
> >> anymore modified (or for only fine corrections, tens of picoseconds).
> >> factory calibration compensates for the delay line and PCB
> >> process/production variations. The boards will operate at almost same
> >> temperature and humidity levels over years of continuous running.
> >> Circuit constrains: The delay line is fed with an AC-coupled LVPECL
> >> output (only P output used) and should provides a single-ended AC clock
> >> output signal.
> >> Indeed, no commercial chip fits into these requirements.
> >> My idea is to use an RC filter to delay the input clock signal and then
> >> restore the clock edges with a LTC6957-1 (LVPECL outputs).
> >> The RC filter would be realized using a varactor (Skyworks
> >> and a 16-bit DAC to control the voltage bias (+ stable voltage
> >> I already checked the values, and sub-ps resolution seems easily
> >> achievable. The solution requires a factory calibration due to the
> >> non-linear behavior of the varactor, but since I only need small
> >> adjustments, this is not a problem.
> >> The problem is to guarantee the calibration over years of operation.
> >> Since a femtofarad parasitic capacitance can change the delay, I already
> >> thought about protecting the delay line with some kind of resin (Epoxy?)
> >> and/or a RF cage to protect it from dirt and moisture.
> >> One of the issue is aging. I derived a typical varactor aging from
> >> oscillators (no varactor manufacturer knows the effects of aging on its
> >> products, apparently) and it's still good. But the aging of LTC6957 is
> >> known.
> >> Is the PCB fabrication using microwave requirements on the dielectric
> >> fine?
> >> Based on your experience, do you think that such delay line can respect
> >> the
> >> requirements listed above, especially stability?
> >> Am I missing something?
> >> Thank you!
> >> cheers,
> >> Mattia Rizzi
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