[time-nuts] Reference input on HP counters

[jimlux]

On 1/7/18 9:55 AM, Jerry Hancock wrote:
> As far as lazy, I will check my equipment.
> 
> When the others that replied using the term “lock” or “locked”, what do you mean by that?  That for instance, the external reference is multiplied up directly to the internal frequency (IF I suppose) or is it phase locked, for instance?  I’m sure there are other cases.
> 
> I’m trying to differentiate between two cases:
> 
> 1) I apply an external reference at 10Mhz (assumed all the devices require 10Mhz at a certain level) and using a switch of some type (electronic or manual) the reference is now multiplied and manipulated directly to feed stages of the device.  In this way, the phase noise of the device is very much dependent on the external reference.  So if a noisy external is used it impacts the device across all time values.
> 
> 2) I apply an external reference and another oscillator, maybe the default or supplied internal 10Mhz (like a 10811, etc) is now EFC adjusted to phase lock to the external reference.  In this way, I would think the phase noise of the device would have been impacted less by the external reference (under the time constant of the PLL or EFC loop.
> 
> Either way, an oscillator with phase issues used as the external reference is going to have some impact on the device, correct?  I’m thinking of in the case where you use a GPSDO that doesn’t have a very good master oscillator.
> 
> Thanks,

I think #1 is the more common traditional approach - the external 
reference "substitutes" for the internal reference. This leads to all 
kinds of discussions about "should I use the counter's internal 
oscillator as the external reference for the spectrum analyzer or vice 
versa" - since counters usually have good AVAR and drift, but don't 
worry as much about close in phase noise, while spectrum analyzers are 
the opposite.

#2 is similar to what's going on inside the 33622, I think.


The differences in ultimate performance depend on what the various 
synthesis schemes are, whether loop based with a PLL or direct synthesis 
with dividers and multipliers.

And even if you know the scheme used in a particular piece of gear, the 
actual behavior is something you basically have to find by 
experimentation (or asking people who have tried it), since 
implementations are always "non-ideal".