[time-nuts] Clock level conversion 5V -> 3.3V

David McGaw n1hac at dartmouth.edu
Wed Oct 1 13:21:50 UTC 2014


Would it not be better for phase noise to use a logic gate with a fast 
transition than a resistive divider that would be slower due to the load 
capacitance?

David


On 10/1/14 7:09 AM, Bob Camp wrote:
> Hi
>
> Ok, so it’s not a super duper low phase noise OCXO. It’s also at a reasonably high frequency.
>
> I’d just drive it into a 5V tolerant input and move on. There are lots of logic gate chips out there that will run from 3.3 and accept 5V inputs. Use something reasonably fast and it will do a pretty good job.
>
> Bob
>
> On Sep 30, 2014, at 10:11 PM, Mark A. Haun <haunma at keteu.org> wrote:
>
>> Hi Bob,
>>
>> The OCXO is one of those 26-MHz ebay Pletronics from a couple years
>> back.  I would like to not degrade its close-in phase noise (quoted as
>> -100 dBc @ 10 Hz, -130 dBc @ 100 Hz).  Thinking about Said's suggestion
>> to phase lock a higher-frequency sampling clock to this, with a loop BW
>> somewhere in the 10-100 Hz range.
>>
>> I have seen a resistive divider used in a similar application, but
>> wondered if I could save the couple dozen mA they were spending.
>>
>> Mark
>>
>> On Tue, 30 Sep 2014 20:18:56 -0400
>> Bob Camp <kb8tq at n1k.org> wrote:
>>> Hi
>>>
>>> How quiet does it need to be?
>>>
>>> Put another way - how good is the OCXO?
>>>
>>> What frequency are we talking about?
>>>
>>> What is the phase noise “need” after you get to 3.3V (is there a
>>> system spec)?
>>>
>>> Bob
>>>
>>> On Sep 30, 2014, at 5:46 PM, Mark Haun <haunma at keteu.org> wrote:
>>>
>>>> Is there a "best" way to do this without adding phase noise?  For
>>>> example, a 5V OCXO into an ADF4002, or a 3.3V or even 1.8V logic
>>>> input.  Is a resistive divider the way to go?
>>>>
>>>> Mark
>>>>
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