[time-nuts] Using CPLD/FPGA or similar for frequency divider

Bob Camp kb8tq at n1k.org
Sat Jun 6 13:52:11 UTC 2015


> On Jun 5, 2015, at 11:19 PM, Hal Murray <hmurray at megapathdsl.net> wrote:
> richard at karlquist.com said:
>> I used a CPLD in a 900 GHz (that's right 900 GHz) optical sampling scope
>> timebase.  It was great because you just write a 17 bit counter in VHDL and
>> there it is.  You don't have to know anything about building digital
>> hardware any more (40 years of experience wasted). Nobody cares about look
>> ahead carry, etc. 
> Is that really true?  

Yes, it’s really true.

> Or perhaps, what fraction of the digital design space 
> does it apply to?

The portion that does not take the design directly to an ASIC. (at
least in industry). Essentially the only thing done with discrete logic
these days are minor i/o chores. 

> How fast was your counter running?
>  How fast would it run?  

That depends entirely on which FPGA or CPLD you buy. An old 100 MHz part will not
go as fast as a 800 MHz part. In this case speed is the toggle rate on the counter. 

> Was it a simple 
> counter or was there enable/up/down/load type gating involved?
> What would you have done if you needed to run a bit faster?

Bought a faster FPGA or gone to an ASIC. 

>  Could you buy a 
> faster chip?  

For enough money there’s always a faster chip :)

> How much more could you get with tricky logic?

The days of “tricky logic” ( =  stuff the software does not understand) are now
the days of “hand place (route) the gates in the FPGA”.  It’s routing delay that
gets you before gate speed in most cases. The software routers have gotten 
awfully good ….

> I agree that modern tools and parts have allowed a lot more people to build 
> digital circuits.

They did that only after they had been allowing mass conversion of designs over
to silicon for about two decades. The tools you see today are nothing like what
you had to use in the early 1990’s. 

The other thing that the design software has done is that it’s forced people to 
face up to timing constraints. Just as in the semiconductor industry, there is now
a “process spec” that is used to constrain the design. If it passes when fully 
constrained and checked, it will work in production. No more blue wires. No more
“oops!” re-spins on $20,000 pc boards. 


> -- 
> These are my opinions.  I hate spam.
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