[time-nuts] Using CPLD/FPGA or similar for frequency divider
watsondaniel3 at gmail.com
Tue Jun 9 00:17:45 UTC 2015
This thread really makes me want to do an FPGA timing project. I have a
Papilio One on hand, which uses the Spartan 3E.
But what to do with it? It has to be something much more interesting than
what a PicDiv or simple logic can do to make it worth my time. Hmm...
On Mon, Jun 8, 2015 at 3:42 PM, cfo <xnews5 at luna.dyndns.dk> wrote:
> On Mon, 08 Jun 2015 16:27:26 +0100, David C. Partridge wrote:
> > I'm up for either ... My thoughts are to try it out on a development
> > board and if it works, maybe build a few for possible sale, and also
> > release Gerbers and VHDL files.
> > Regards,
> > David Partridge
> I have these cheap cards , that might be a nice start.
> CPLD Altera EPM240 (make sure you get the blue board)
> Ebay: 271520142479
> Fpga (2 onboard PLL's) older Cyclone2 , but prob ok.
> Ebay: 400630255386
> Ebay: 200943750380
> If they could be the heart of the system, then everybody could get
> started cheap.
> I'm using Quartus2 on Linux (Mint17) , works ok.
> But Modelsim needs some extra libs to function.
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