[time-nuts] Using CPLD/FPGA or similar for frequency

Bob Camp kb8tq at n1k.org
Thu Jun 11 11:11:40 UTC 2015


Depending on which chip you are using and how big it is, you can get into the 150 to
500 ps range running a carry chain as a TDC.That’s without getting into things like
hand routing and temperature / voltage issues. 

How big a chip you need will be a function of how high you can get the internal PLL
to run while packing a bunch of stuff in the chip. If you can hit 400 MHz, each carry 
chain will need to handle a bit more than 2.5 ns, but probably less than 5 ns. You 
can do that with a carry chain a few hundred bits long. 

There is a bit of handwaving already so this is indeed a guess rather than a design. 
If you run 320 bit chains and 8 inputs, you will need 2.5K registers for the carry chains. 
You also will need about 200 registers for the support of each chain, so that adds another
1.6K registers. Something in the 5K register range is a possible way to go for 8 inputs.

> On Jun 11, 2015, at 2:04 AM, Gregory Maxwell <gmaxwell at gmail.com> wrote:
> On Tue, Jun 9, 2015 at 11:40 AM, Alan Ambrose <alan.ambrose at anagram.net> wrote:
>> How about a 1pS resolution TIC? :)
>> Or a >12 digit frequency counter? :) :)
>> It's not a proper time-nut project unless there's a nutty element...
> Well, how complex? Front end with a fast ADC and make a DSP DMTD device?
> In terms of simpler things that (AFAIK) one can't go out and buy:  a
> TIC with 4 or 8 inputs would be an interesting piece of time nut
> gear.even if it was 'just' 1ns resolution
> Surplus lab TICs are easily had but become quite a pile of equipment
> when you want to concurrently measure a half dozen oscillators.
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