[time-nuts] Using CPLD/FPGA or similar for frequency
attila at kinali.ch
Tue Jun 16 08:01:09 UTC 2015
On Tue, 16 Jun 2015 12:24:34 +1200
Bruce Griffiths <bruce.griffiths at xtra.co.nz> wrote:
> Using an ADC to sample a triggered damped sinewave easily achieves 5ps
> resolution (eg Keysight Acquiris). With a better optimised waveform model
> and least squares fitting routine greater resolution is feasible.
> The accuracy is dependent on the ADC sampling clock stability.
> An optical frequency standard derived clock may be required to maintain
> ps accuracy for long time intervals.
Do you mean the technique that Panek et al.  are using?
IIRC he got that down to 0.5ps RMS now. And yes, the major
source of error is the oscillator, according to .
Ripamonti et al. showed in  that using an LC tank instead of an SAW
filter will result in something in the order of 2-10ps RMS (after
temperature compensation). So this system is in the same region as an well
designed time-to-amplitude converter based system.
I really wonder which one would be easier to build.
 "Time interval measurement device based on surface acoustic wave filter
excitation, providing 1ps precision and stability", by Panek andProchazka, 2007
 "Random Errors in Time Interval Measurement Based on SAW Filter Excitation",
by Panek, 2008
 "High frequency, high time resolution time-to-digital converter employing
passive resonating circuits", by Ripamonti, Abba, Geraci, 2010
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