[time-nuts] Timelab, two SR620s and losing samples

Magnus Danielson magnus at rubidium.dyndns.org
Sat Jan 16 05:00:54 UTC 2016


On 01/14/2016 03:38 PM, Attila Kinali wrote:
> Moin,
> I have here a setup with four (FPGA) nodes that produce synchronized pulses
> with a 20kHz rate. I have two SR620s two measure those pulses.
> Because the SR620s are not fast enought to capture all pulses, and because
> i want them to be synchronized, I set up one of the nodes to generate an
> additional pulse every 100ms (10Hz rate) 20us before the "main" pulse,
> and feed that to the two EXT trigger inputs of the SR620s.
> The two SR620s are both connected to an FS725 Rb frequency standard
> (mostly because we have them around and nobody else uses them :-)

It's being used, by you! ;-)

> Now, I use Timelab (running on Windows XP, in a virtualbox on a linux system),
> using two serial-to-USB converters (FT232), which are passed as raw USB
> devices into windows. Capturing both SR620s together in timelab, I see
> one of the SR620s "producing" less samples than the other.
> Quite considerably less (it looks like 1-3% less or so).
> I have already checked and rechecked the trigger settings, the trigger
> voltages etc, but I cannot find why one produces less samples than the other.
> I have changed cables, swapped nodes. But it's still the same SR620 that
> loses samples.

Have you tried swapping "role" of the SR620?
Have you tried grabbing data in the Linux environment?
Consider that the virtual box thing might not have the cleverest method 
to handle data from multiple serial devices.
Have you tried swapping the serial-to-USB adaptors?
Have you tried grabbing data on two independent PCs, just to avoid 
issues in the USB handling? (Yes, never mind it won't correlate, just 
check that you get the same amount of data)
Have you tried feeding timelab two streams generated on the linux side?

Essentially, from the counters to TimeLab you have a weak link, and you 
need to consider all parts of it to identify which of them that is the 
weak link.

> Another curious thing I see that I couldn't make sense of is, that from
> time to time, on both of the SR620s, I see time differences of 1s (yes,
> one full second). Given that the FPGAs produce a pulse every 50us, this
> shouldn't be possible, unless the crystal oscillator stops.
> Any idea what I might have done wrong or what the cause is?

It's not a consequence of the TI +/--mode such that the stop trigger 
gets in early and you get a negative value reported because it takes 
(start-time) - (stop-time) but allowing the stop-time to be the first?
Check the raw data.


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