[time-nuts] Re: Phase accuracy of multiple output frequency picDIV

[Hal Murray]

Erik Kaashoek said:
> Is this phase shift to be expected from all multiple output frequency
> picDIV's ? 

Yes.

The problem area is well known to digital geeks.  The buzzword is
  Simultaneous Switching Outputs, or SSO

The basic problem is that there is shared impedance in the power/ground 
circutiry to the driver transistors in the output pads.  For high speed logic, 
the inductance becomes critical.

Consider 5V CMOS logic.  Assume a driver turns on switching from low to high.  
It is charging the capacitace of the pad and driving the output transmission 
line.  That takes some current.  There is impedance in the power supply.  
Suppose the numbers work out such that the driving transistor only gets 4.9 
volts.  Now turn on two of them.  They will only get 4.8 volts.  That turns 
into slightly slower rise times...

This is why bus driver chips often have multiple power/ground pins.  Same for 
VLSI and FPGAs.  I think it's reasonably well known that if you are using an 
FPGA to generate a clock and you want a good clean clock, for example to drive 
an ADC feeding software radio, that you have to waste the rest of the FPGA.


It would be fun to get some good scope pictures from a PIC.
(That sounds like a rat hole, but I'm retired.)

If I was doing it, I would probably write some special PIC code.  The idea is 
to wiggle the pins in an interesting pattern, then wait a while so the scope 
is ready, then wiggle the pins in a different pattern so you get two cases 
overlaid.  Or something like that.

Repeat with better/worse pwr/gnd bypassing.



-- 
These are my opinions.  I hate spam.