[time-nuts] DMTD Questions

[Chris Hastreiter]

Time-nuts,

I have been working on some modifications to Corby’s DMTD design [1] in an
effort to further improve its noise floor and had a couple questions for
the group.  The performance I’ve been able to achieve so far is shown in
the below plot with the blue trace being the noise of the ProTIC counter
itself, the pink trace being the combined noise of the counter and my zero
crossing detector (both channels driven by a 10Hz sine wave), and the
remaining traces the full system noise floors with 4 different offset
oscillator options.  All noise floor measurements were taken with a carrier
frequency of 10MHz and an offset of 10Hz.  I believe that much of the noise
floor degradation at long tau is due to thermal effects in the first stage
amplifier of the ZCD as I haven’t yet gotten the system installed into an
enclosure and I can worsen the issue by thermally disturbing the LT1028 of
the first stage.

[image: image.png]

My first question is in relation to mixer noise which is a noise source
that I have not yet considered.  I am using the same SBL-1 mixer as Corby’s
original design but [2] implies that some mixers exhibit lower flicker
phase modulation than others and I haven’t seen any literature or
specifications that point to any devices other than the 10514A in that
paper.  They also discuss adding capacitive loading to the mixer to further
reduce noise referencing another paper that I have yet to be able to find.
Is there any expectation that changing to a mixer different than the SBL-1
will improve my results and should I consider capacitive loading on the
mixer?  If so, how would I determine an appropriate amount of capacitive
loading?  I currently have it loaded with a bridged-T filter holding 50
Ohms of impedance across the frequency spectrum.



My second question is in regard to the common oscillator noise
contribution, specifically for the use case of a synthesized offset
oscillator.  The below plot shows the results I’ve gotten so far with some
sources that I already have, and as can be seen the system noise floor
degrades much faster with the synthesized offset than with the 10811A.
However, it would be advantageous for me to be able to use a synthesized
offset for tests where the DUTs differ slightly in frequency and the system
will phase wrap.  The reason for this is that when using a free-running
oscillator the phase wraps are very difficult to remove automatically
because the divided phase wrap will differ from the expected with any
frequency error in the offset oscillator.  Do you have any suggestions for
synthesizers or other offset techniques that would help with this?  Using a
10811A and a slow PLL as a cleanup loop on the synthesizer does appear to
work well in the below plot, but looking at the first plot in this email at
least in my initial implementation there seems to be some low frequency
oscillation in the PLL impacting the noise floor.  I’ve also included a
plot showing measurements I’ve taken of the residual noise for the two
synthesizers used as well as a comparison of two of the 10811A oscillators
that I’m using.

[image: image.png]

[image: image.png]

[1] https://www.eevblog.com/forum/metrology/dmtd-board/

[2] https://ieeexplore.ieee.org/document/5075023



Thanks,



Chris
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