  hasweb@has.org.nz wrote:

  >Mike

  > You could always look at: United States Patent US4820939.

  > But dont bet on it.

  >Bruce

  There's lots of them. I don't believe them.

  Philips even  has  one on their 74F50729:  US5,789,945.  I  have not
  tried it but some reports say it doesn't work.

  OTOH, I used the digital mixer described previously to lock as close
  to the  metastability  condition of a flip-flop as  possible  for my
  second patent.

  The circuit  tried to lock on logic level 0.5, but  of  course could
  never accomplish  this task. But this tied the edge of a delay  to a
  reference so I could measure the offset and window width in the data
  separator with a TIA.

  The circuit  used Motorola MECL 10KH ECL. I could  see  the attached
  waveforms on  my  Tek 7104 fairly often. It was  barely  possible to
  measure the  jitter  between the clock and d inputs with  a  HP 5370
  TIA. I don't remember the value but it was quite small.

  Later I  upgraded to Motorola EclInPs. Using the  same  circuit, and
  others like it, I could no longer get any metastability condition on
  a MC100EP52 D flop no matter how hard I tried.

  So the faster chips really are difficult to get into a metastability
  condition. But  I continue to use cascaded shift  registers  to keep
  them at bay.

  Best Regards,

  Mike Monett
