>I filed patent 3,810,234 on Aug 21, 1972. It includes a dual-d pfd with
>variable delay in the feedback path to eliminate deadband. The term
>deadband is not included in the patent since it did not exist at the time.

Sorry, I was mistaken. I explain dead-band on Page 9 of the patent:

"The basic configuration of the phase detector 20 includes two
D-type flip-flops 24 and 26 with feedback to restore both to the
initial state after both have been clocked. A delay 28 in the
feedback path 30 establishes the minimum time that either flip-flop
is in the clocked state, thus establishing a minimum time that
current sources 21a and 21b are switched on. Delay 28 is selected to
insure that both current sources 21a and 21b are first turned fully
on before they are turned off. This feature is necessary to
eliminate dead-band whereby the phase detector 20 does not respond
properly to small phase errors (or time differences) between the two
input signals to the phase detector 20."

This explanation is accurate for symmetrical charge pump delays. The
deadband in the MC4044 is not symmetrical. The DF delay is caused by a
transistor being slow coming out of saturation. This could have been
prevented by applying a Baker clamp around the transistor, or by simply
using diodes to switch the charge pump as was done by CR1 for the UF path.

The transistor in question is Q2 shown on page 5 of the attached MC4044
datasheet.

Also note the DF and UF outputs are shorted together in the datasheet. This
creates a short across VCC on every cycle as both are turned on to reset
the latches.

>The google url is

>https://patentimages.storage.googleapis.com/53/fc/f0/26d83e477e999a/US3810234.pdf

>Mike Monett