[time-nuts] Locking 100 MHz to 10 MHz

Bruce Griffiths bruce.griffiths at xtra.co.nz
Wed Dec 19 14:56:26 EST 2007


Matt Ettus wrote:
> - Second, for when there is no 10 MHz reference connected, the system
> needs to be brought to a reasonable frequency.  The PLL charge pump
> outputs are tri-stated.  On the end of the loop filter, right before
> the control voltage input to the VCXO, I have a resistor divider to
> center the voltage between 3.3V and ground.  I use 100K resistors in
> the hope that they will not affect things when the loop is active, but
> I can't really tell, since all the phase noises involved are well
> below the ability of my equipment to measure.  Is this a safe
> technique, or am I messing up the performance while the loop is
> locked?
>
> Thanks,
> Matt
>
>   
Matt

Use an SPDT analog switch to connect the 100MHz EFC to either the PLL
filter output or to whatever voltage required to centre the 100Mhz
oscillator frequency.
Could be a low impedance pot, resistive divider DAC output etc. Use
large C to ground at pot wiper (or divider tap) to minimise noise.
Use a diode detector and a comparator to check if the external 10MHz
input is present.
If the 10MHz is present switch the EFC input to the filtered PLL ouput.
If the 10MHz signal isnt present switch the EFC to the filtered divider
(or pot wiper or DAC) output.

Buce




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