[time-nuts] Metastability in a 100 MHz TIC

Dr Bruce Griffiths bruce.griffiths at xtra.co.nz
Fri Jul 20 22:52:00 EDT 2007

Tom Van Baak wrote:
>> The simpler and cheaper D 
>> flipflop precedence detector used together with hardware sawtooth 
>> correction has far higher resolution. It also has the advantage of not 
>> requiring any high frequency clocks.
>> Bruce
> Since Rick & Dr TAC brought it up some months ago, does
> anyone have measurements for this approach yet?
> Also what is its equivalent resolution; i.e., what resolution
> would a conventional TIC need to be to match the behavior
> of the D-flipflop approach, all other factors equal?
> /tvb

With say a 2ns rms noise on the corrected PPS output, a TIC would need 
an rms quantisation noise less than 1/3 of this to avoid significantly 
degrading the measurement noise.
The corresponding TIC resolution would be about 7ns (140MHz). However to 
achieve accurate averaging the required rms jitter at the TIC input is 
around 1 clock period which implies that a TIC clock period of around 
2ns (500MHz) is required. If the receiver timing noise is greater then a 
lower frequency clock can be used. The D flipflop approach produces a 
degradation of less than 2dB with respect to an ideal TIC with infinite 
resolution. The other advantage is that such a 1 bit TIC automatically 
adapts to the timing noise that is present.

The most cost effective way of achieving perhaps a dB or so improvement 
is to use an ADC as a TIC, sampling an input sinewave produced by 
dividing down and low pass filtering the output of the OCXO on the 
leading edge of the PPS signal. A resolution equivalent to using a 1GHz 
or faster clock is easily achieved. The cost of suitable ADCs is 
relatively low.

Neither of these solutions requires using clocks faster than 10MHz or 
so. Nor are particularly esoteric high speed logic devices required. 
Although ACMOS devices are desirable, even HCMOS devices should be 
satisfactory, particularly if given 200 millisec to resolve any 
metastable state.

The circuit schematic attached also provides 100ns (with a 10MHz clock) 
guardbands either side of the edge that is locked to the hardware 
corrected PPS signal.
For example U103 3Q, 4Q, 5Q are used as precedence detectors the PPS 
being locked to  U102 Q4 with  Q3 and Q5 acting as guardbands 
transitions to allow detection of when the PPS leading edge is 100ns or 
more away from  the transition on U102  Q4. This allows rejection of 

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