[time-nuts] time-nuts Frequency Divider

Fri Apr 3 03:15:07 UTC 2009

Mike Monett wrote:
>   > Message: 8
>   > Date: Fri, 03 Apr 2009 12:28:31 +1300
>   > From: Bruce Griffiths <bruce.griffiths at xtra.co.nz>
>   > Subject: Re: [time-nuts] time-nuts Frequency Divider
>
>   > Mike
>
>   > The problem is more accurately described as:
>
>   > When the bias network dc level at the 74AC04 (or  74HC04) inverter
>   > input isn't  equal  to the switching threshold  of  the particular
>   > device then  AM  modulation on the input  signal  is  converted to
>   > phase noise as switching no longer occurs at the zero  crossing of
>   > the input signal.
>
>   The problem is adequately described in my article. I show  the AM/PM
>   conversion in "Fig 3. Threshold Switching", in
>
>   http://pstca.com/spice/74ac04/limiter.htm
>
>   > Such behaviour  is inherent when using a  Schmitt  trigger circuit
>   > and it cannot be cured with a feedback circuit that stabilises the
>   > output duty cycle.
>
>   The 74AC04  and 74HC04 are not Schmitt triggers, and  are  useful as
>   limiters as discussed here previously. The +/- 30% tolerance  on the
>   switching threshold  applies to the 74XX04 and pretty  much  all the
>   CMOS gates  and  flops  as  well. It  is  an  inherent  problem with
>   matching N and P channel mosfets.
>   

No one said they were,
However a previous post mentioned using schmitt triggers.
I was merely pointing out that a feedback duty cycle stabiliser won't
eliminate the AM to PM conversion characteristic  inherent with a
Schmitt trigger device.
>   However, in any limiter, the duty cycle must be controlled  to avoid
>   AM/PM conversion,  not just the 74XX series. This problem  is solved
>   with the feedback method described in my article.
>
>   
Which is not necessary if one is using a good OCXO with low AM output noise.
Well designed OCXOs tend to have very low AM noise.
>   One of  the surprises is the circuit is remarkably stable  even with
>   huge changes in loop gain. I describe this near the bottom.
>
>   The 74XX14  is  a  Schmitt trigger,  and  it  will  have unavoidable
>   problems with  AM/PM  conversion.  I mention  this  in  the section,
>   "Cascading 74AC04's  For More Gain", about 2/3 of the  way  down the
>   page:
>
>   http://pstca.com/spice/74ac04/limiter.htm
>
>   If the limiter has hysteresis, you can minimize AM/PM  conversion on
>   one edge, but not both.
>
>   > A well  designed  limiter  +   filter   cascade  in  front  of the
>   > comparator, Schmitt trigger or logic gate can be used  to minimise
>   > such AM to PM conversion whilst minimising the output jitter.
>
>   It doesn't  matter  what  you put in front  of  the  limiter. Adding
>   another one  in front just moves the problem  further  upstream, and
>   adds more phase noise.
>
>   
Nonsense, it has been shown (during the 1990's) that if designed
correctly (with an appropriate and well defined gain and filter cutoff
frequency for each limiter stage) a cascade of limiters and low pass
filters works much better than merely cascading a series of limiter
stages with ill defined gain either with or without an input threshold
stabilisation feedback loop.
>   Unless the  switching threshold in the limiter is controlled  to set
>   the duty cycle to 50%, you will have problems with AM/PM conversion.
>   Also, it  might be desirable to add some voltage trim  to compensate
>   for harmonic distortion.
>
>   > Bruce
>
>   Mike
>   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>   Here is the response to your next post to save time:
>
>   > Mike
>
>   > Its well  worthwhile  estimating the additional jitter  due  to this
>   > effect when using such a circuit to square up the output of an OCXO:
>
>   > If the input signal characteristics are:
>
>   > Frequency 10MHz  Amplitude at the gate input: A = 1.4V  pk Threshold
>   > mismatch Vt  =  1V AM noise: Am = -120dBc/Hz Input  signal  AM noise
>   > bandwidth: BW = 1MHz (eg a low Q bandpass filter).
>
>   > Rms Output jitter due to AM noise is given by
>
>   > delta(t) ~ (1/(2*PI*f))*((Vt/A)/(1 + (Vt/A)*(Vt/A)))*(BW*1)^(Am/20))
>
>   > i.e.
>
>   > delta(t) ~ 0.5*1.6E-8 *(1E-3) sec ~ 8ps rms.
>
>   > Wideband AM  noise as high as -120dBc/Hz is somewhat higher  than is
>   > typical for a good OCXO.
>
>   > Thus in  applications such as a PPS divider this effect  is probably
>   > insignificant.
>
>   > However it may be useful to use a low Q bandpass filter to limit the
>   > integrated AM and PM noise seen at the gate input.
>
>   > Bruce
>
>   I did  not  have time to check your math.  However,  8ps  rms jitter
>   would be unacceptable in many applications.
>
>   
In practice it will be much smaller than that with a good OCXO.
When using a  divider to compare the frequency of an OCXO with the PPS
output of a GPS timing receiver a jitter of 8ps is insignificant.
If one uses a typical CPLD or FPGA to implement a divider without any
external retiming flipflops the typical output jitter is much larger
than 8ps.
A CPLD or FPGA with LVDS outputs and inputs may have somewhat lower jitter.
>   A low  Q bandpass filter has been discussed here often.  It  may not
>   help the  jitter  until the bandwidth is quite narrow,  and  it will
>   cause other problems with drift due to aging and tempco.
>   
The effectiveness of the filter depends on the AM  (and PM )noise
spectrum, if this is very broad then even a low Q bandpass filter will help.
With a good OCXO the broadband AM (and PM) noise is low and filtering
isnt usually required.
>   I am  unfortunately very busy at the moment, and will not  have time
>   to follow this thread further.
>
>   Mike
>
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