[time-nuts] time-nuts Frequency Divider

Bruce Griffiths bruce.griffiths at xtra.co.nz
Fri Apr 3 21:16:01 UTC 2009


I forgot to include the intrinsic jitter of the gate in the calculations.
See underlined corrections below.


Bruce Griffiths wrote:

> Magnus
> The input noise of a logic inverter or other trigger device used as a
> clock shaper is important.
> If we have a logic inverter device with the following characteristics:
> Input noise: 100uV rms
> Intrinsic jitter: 1ps rms
> Then the input signal slew rate at the threshold crossing has to be
> greater than
> 3x1E-4/1E-12 = 3E8 V/s or 300 V/us
> to ensure that the output jitter isnt increased by more than 5% from the
> intrinsic jitter.
> With a 1.4V pk 10MHz sinewave input the maximum slew rate is ~89V/us (at
> the zero crossing).
> For such an input signal the output jitter will be about _1.5 ps_.
> This increases to about _1.72ps_ if there is a threshold offset of 1V.
> This can be reduced to about 1.05ps by amplifying the slope of the input
> signal by ~ 3.4x.
> The intrinsic jitter (RJ. DDJ isn't important when the input signal is a
> low distortion sinewave) of a 74AC04 inverter is about 1ps.
> However the equivalent input noise is unknown.
> The noise could, in principle, be determined by measuring the output
> jitter as a function of the input signal slew rate.
> Whilst AM and other noise associated with the source can be reduced by
> filtering, the input noise of a trigger circuit cannot (except perhaps
> for the trigger circuits input current noise).
> Magnus Danielson wrote:
>> Bruce Griffiths skrev:
>>> Ulrich
>>> Your experience with the SR620 illustrates the point I was making quite
>>> well.
>>> It really does matter what you do in front of the limiter circuit built
>>> into the counter.
>>> A bandpass or any other filter by itself is ineffective unless the
>>> signal is exceptionally noisy.
>>> By using the inverter in the 74HCT4046 you have added a low gain limiter
>>> stage the bandwidth of which is smaller than that of the SR620 input
>>> circuit.
>>> This has the effect of increasing the slew rate of the input signal
>>> whilst producing an output with less jitter than the SR620 input circuit
>>> would without this low pass filtered limiter circuit (the inverter from
>>> the 74HCT4046). The slew rate at the 74HCT4046 inverter output is
>>> greater than that of the input signal which means that the jitter due
>>> the counter input circuit noise is smaller than when this low gain low
>>> bandwidth limiter isn't used.
>>> The input circuit of the SR620 has a wide noise bandwidth (~ 470MHz
>>> assuming a single pole response with a 300MHz 3dB high frequency cutoff)
>>> and a correspondingly high total input noise (~350uV rms).
>>> If the slew rate of the SR 620 input signal at the trigger point the
>>> jitter due to this noise dominates the trigger circuit output jitter.
>>> The HP5370 time interval counter input circuit has a lower noise
>>> bandwidth (~160MHz??) and is quieter (~ 100uV rms) than the input
>>> circuit of the SR620 and thus the HP5370 jitter (without the 74HCT4046
>>> limiter) for the same 10MHz signal should be less than that of the SR620
>>> (without the 74HCT4046 limiter).
>> As a curiosity, there are various variants of the original 4046 which 
>> has different sensitivity on the input side... one of them has several 
>> inverters in a row to get the needed gain where as the other variant 
>> does not. This difference made a huge difference in some applications.
> The appropriate device (one that will have the least output jitter) to
> use will vary with the input signal zero crossing slew rate.
> That is it depends on both the input signal frequency and amplitude.
>>> If one uses a state of the art trigger circuit with a noise bandwidth of
>>> 1GHz or more then the total input noise will be even larger so it
>>> becomes even more important to use an optimised cascade of limiter+ low
>>> output pass filter stages to increase the slew rate of the counter
>>> input  trigger circuit at the trigger threshold.
>>> Careful optimisation of the gain of each stage and the corresponding
>>> output filter cutoff frequency for each stage is necessary to minimise
>>> the output jitter of the counter trigger circuit.
>>> There is also an optimum number of such stages that minimises the
>>> trigger jitter.
>>> The optimisation problem for Limiter stages with gaussian wideband input
>>> noise was solved in the 1990's.
>>> Unfortunately the optimum number of stages, associated gains and output
>>> filter bandwidths depends on the input signal frequency and amplitude so
>>> that in general it isn't possible to use the same limiter cascade for a
>>> wide range of signal amplitudes and frequencies and minimise the jitter
>>> for each frequency and amplitude.
>> Actually, you can make a cascade setup which is approaching optimum and
>> insert signal at the stage where the signals slewrate matches the range 
>> for each stage. Since the gain steps is larger later in a slew rate 
>> amplifier chain, the last stages may have a little coarse slew rate 
>> range, but additional mid-range amplifiers that can act as alternative 
>> input amps could curcumvent that such that a wide range but and fairly 
>> good trigger jitter could be achieved.
>> The comparator level is fed to whatever stage is the first stage.
>> Such an approach could lead to much improved jitter values for lower 
>> frequency signals with associated gain in measurement accuracy.
>> It is easy to make a pre-amplifier set that achieves this, but you want 
>> to integrate the control algorithms for automatic use.
> That would constitute an interesting design challenge.
>>> Thus such circuits aren't usually employed in general purpose frequency counters.
>> Certainly true. A generic counter is usually equipped with triggers such 
>> that they can measure slewrate without too much difficulty.
>>> However if the input signal frequency and amplitude are known and stable
>>> then using such a limiter filter cascade is feasible.
>> Indeed.
>> Cheers,
>> Magnus
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> Bruce
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