[time-nuts] femtosecond jitter anyone?
magnus at rubidium.dyndns.org
Wed Apr 8 22:14:45 UTC 2009
Chris Mack / N1SKY skrev:
> Hey Magnus,
> This is a good idea for testing..
Applying jitter frequencies for jitter tolerance testing is standard
stuff and needs to be done. Jitter tolerance curves match up with MTIE
tolerance curves very neatly.
> I have Howard Johnson's book for
> "high speed digital design (a handbook of black magic)" which shows
> some circuits with varactors on the transmission line with some ECL
> gates creating a variable delay based on an analogue voltage... maybe
> that could work before filtering into a sine....
I think a normal LC tank would be more suitable for that task.
It's a good introductional level book for digital signals, but isn't
very applicable to waveshaping or clock characterisation and testing.
> The DSP ultimately has 3 ports where the jitter reference (pins XA
> and XB differential sine or square) is one port for the digitally
> controlled oscillator (and also the clock to run the DSP), then the
> remaining 2 ports for input clock (CLK_IN) and the output (CLK_OUT)
> generated clock (any frequency really based on PLL coefficients).
I still don't understand what you want it to do... or what it is
supposed to do and what jitter reference means in your context, low
jitter or know jitter.
> It is roughly 1:1 jitter transfer from jitter reference (38,88MHz) to
> output clock, regardless of CLK_IN but for only a certain bandwidth,
> 12kHz to 20MHz or so; It gets better, slightly, when looking close
> into the carrier but ultimately this jitter reference is used to
> clean an input clock on other pins for the outgoing PLL generated
Sounds like a locked oscillator with PLL bandwidth of 12 kHz. The jitter
of the locked oscillator is high-pass filtered by the PLL loop.
> The same circuit could also be used outside of testing the jitter
> reference I suppose and be used on the incoming clock to be cleaned
> signal too....
> Yes, it may actually be ideal to put jitter on the incoming clock to
> be cleaned... With added jitter on the incoming clock to be cleaned,
> it may keep the PLL out of the dead zone and ultimately force it do
> some useful work at all times rather than coast/drift in said dead
> zone.... But what shape of jittter to be introduced (noise shape on
> the proposed analogue voltage perturbing the varactors)? hmmmmm....
If you have a dead-zone on your PLL you need to fix it. I have learned
the hard way that dead-zone PLLs can cause significant jitter/wander
since they will get very abrupt shifts of direction in each end of the
dead-zone. When using detectors (every simple ones like SR-FF) which
does not have dead-zones it becomes feasible to tune it properly.
Continuous detector and active filter for PI regulation should be the
standard approach most of the times. Not hard and expensive to achieve
by todays standards IMHO.
May I stress that when doing SDH/SONET this is of particular importance.
> Still trying to figure out crystals for filter purposes though since
> any documentation I have on crystals shows a typical circuit with
> logic gates to make a clock to feed a microprocessor (different from
> what I need it to do of course since I already have an OCXO)....
It's actually not that hard to figure out. If you model a crystal as an
LCR chain in parallel with a C then you have a model for an oscillator
and a single mode. several LCR chains in parallel is needed if multiple
modes needs to be modeled/simulated.
Crystal filters build upon these types of models. I still don't think
you need to revert to crystal filters. If you just want to sine up a
squarewave, a simple LC tank may be just want you need. A CLC or CRC
PI-filter may also suite your needs more than sufficiently.
If you need very high Q filters for a fairly fixed frequency, crystal
filters may be used, but PLLs may also be part of the solution, as you
can see them as a form of self-retuneable bandpass filter.
More information about the time-nuts