[time-nuts] femtosecond jitter anyone?
Chris Mack / N1SKY
sometimesyoufeellikeanut at twentylogten.com
Wed Apr 8 21:45:34 UTC 2009
This is a good idea for testing.. I have Howard Johnson's book for
"high speed digital design (a handbook of black magic)" which shows
some circuits with varactors on the transmission line with some ECL
gates creating a variable delay based on an analogue voltage... maybe
that could work before filtering into a sine....
The DSP ultimately has 3 ports where the jitter reference (pins XA
and XB differential sine or square) is one port for the digitally
controlled oscillator (and also the clock to run the DSP), then the
remaining 2 ports for input clock (CLK_IN) and the output (CLK_OUT)
generated clock (any frequency really based on PLL coefficients).
It is roughly 1:1 jitter transfer from jitter reference (38,88MHz) to
output clock, regardless of CLK_IN but for only a certain bandwidth,
12kHz to 20MHz or so; It gets better, slightly, when looking close
into the carrier but ultimately this jitter reference is used to
clean an input clock on other pins for the outgoing PLL generated
The same circuit could also be used outside of testing the jitter
reference I suppose and be used on the incoming clock to be cleaned
Yes, it may actually be ideal to put jitter on the incoming clock to
be cleaned... With added jitter on the incoming clock to be cleaned,
it may keep the PLL out of the dead zone and ultimately force it do
some useful work at all times rather than coast/drift in said dead
zone.... But what shape of jittter to be introduced (noise shape on
the proposed analogue voltage perturbing the varactors)? hmmmmm....
Still trying to figure out crystals for filter purposes though since
any documentation I have on crystals shows a typical circuit with
logic gates to make a clock to feed a microprocessor (different from
what I need it to do of course since I already have an OCXO)....
On Apr 8, 2009, at 5:09 PM, Magnus Danielson wrote:
> Chris Mack / N1SKY skrev:
>> Hello fellow time nuts,
>> Have a project here with an OCXO from Vectron at 38.88MHz being the
>> "jitter reference" for a DSP based PLL.
>> The Vectron part has a little bit of close-in phase noise below 12kHz
>> of BW. Is there a way to filter this, say by driving an external
>> (temperature stabilized) crystal "backwards" (in the non-traditional
>> sense rather than using the crystal to provide a clock for a system)
>> and recovering the signal?
>> Also the output of the Vectron part is square and it would be ideal
>> to distribute a sine wave....
>> I cannot find traditional crystal filters that have a direct center
>> at 38.88MHz also with any usable bandwidth (for the close-in skirt)
>> for this application.
>> The DSP PLL has "femtosecond" jitter capabilities depending on how it
>> is applied, e.g., for SONET and the like and also depending upon
>> measurement BW used. Also the jitter reference comes into play here
>> as well....
>> For the sampling application this is being used for, it would be
>> ideal (by design) to keep the timing uncertainty below 0.45ps or
>> Any thoughts?
> Do you want to apply jitter to the 38,88 MHz clock?
> In particular, do you want to be able to modulate it with various
> amounts of sine in order to test jitter tolerance (a common SDH/SONET
> Essentially you want phase modulations for those purposes. You can
> them on the output signal for smaller amounts, but for larger
> it is not as convenient. Tolerance modulations may need to be several
> cycles peak-to-peak. A combination of phase modulation and frequency
> modulation can be used. One approach is to phase lock the
> oscillator to
> a reference and insert the modulation signal into the PLL loop.
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