[time-nuts] DDS'ery narrow scoped.

[Javier Herrero]

Hello,

El 21/06/2011 02:19, Luis Cupido escribió:
>
> Imagine an FPGA and a square wave coming out.
> Just that. Nothing more.
>
> (That is what I had in mind when querying about the MSB usage in
> the first place.)
>
>
> My first approach was the ACC MSB
> (and that is working already on the bench.)
>
>
I supppose that then you will need the digital version of the DDS -> 
Filter -> Comparator think, usign a FIR and outputing the sign of the 
resultant signal.
>
>
> P.S. At the moment I'm testing on the bench with a real FPGA cyclone III
> with a 48bit dds at 100MHz fclock and at circa 6 and 18MHz output and 
> it is not that bad. I got better than -60dBc in the desired ranges.
> So not too unhappy for a start ;-) PLL cleans 99% of it...
> but the close in spurs are annoying.
>
>
What it the topology you're using now? Also, I would like to know which 
DDS core are you using? (since I will need to use one quite soon, 
probably on a Cyclone IV E)

Best regards,

Javier

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-- 
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Javier Herrero                            EMAIL: jherrero at hvsistemas.com
Chief Technology Officer
HV Sistemas S.L.                          PHONE:         +34 949 336 806
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