[time-nuts] Looking for ECL divide by 3 with symmetry

Robert LaJeunesse lajeunesse at mail.com
Sun Sep 27 21:28:42 EDT 2015


IIRC one would use a divide by 4 circuit with the final output feeding back to an exclusive-or gate through which the (square wave) source clock passes. The ex-or effectively adds a clock edge to the divide by four, making it divide by three. It also changes the effective clock edge, so the final output is basically a square wave.

http://www.theremin.us/Circuit_Library/symmetrical_digital_dividers.html

Bob LaJeunesse

> Sent: Sunday, September 27, 2015 at 12:36 PM
> From: "ed breya" <eb at telight.com>
> To: time-nuts at febo.com
> Subject: [time-nuts] Looking for ECL divide by 3 with symmetry
>
> I need to build an ECL divide by 3 circuit to run at about 50 MHz input. 
> I know there are lots of examples out there, but I vaguely recall years 
> ago I stumbled upon one or more that also provided more of a symmetrical 
> output nearly 50 percent duty factor, by using both input edges, or 
> reclocking with another FF. I saved the info, but of course can't find 
> it now that I need it - in my computers, papers, or online. Does anyone 
> know of these tricks, and any example circuits - this would save me some 
> rediscovery and design time.
> 
> Ed
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